Abstract: A multi-phase power switching converter having first and second states includes a pulse width modulator having an output, a converter output providing an output signal, and a plurality of drivers, each having an output electrically coupled to the converter output and an input. When the converter is in the first state where a duty cycle of the converter is less than or equal to 100 divided by the number of drivers, each of the driver inputs is configured to be sequentially electrically coupled to the pulse width modulator output. When the converter is in the second state where the duty cycle of the converter is greater than 100 divided by the number of drivers, each of the driver inputs is simultaneously electrically coupled to the pulse width modulator output.

Abstract: A multi-phase power switching converter having first and second states includes a pulse width modulator having an output, a converter output providing an output signal, and a plurality of drivers, each having an output electrically coupled to the converter output and an input. When the converter is in the first state where a duty cycle of the converter is less than or equal to 100 divided by the number of drivers, each of the driver inputs is configured to be sequentially electrically coupled to the pulse width modulator output. When the converter is in the second state where the duty cycle of the converter is greater than 100 divided by the number of drivers, each of the driver inputs is simultaneously electrically coupled to the pulse width modulator output.

Abstract: An improved push-pull amplifier having a driver circuit for driving a source follower output transistor. The driver circuit includes a replicating transistor having electrical characteristics substantially similar to those of the source follower transistor, a buffer amplifier, and a circuit, coupled to the replicating transistor and the buffer amplifier, for summing the voltage across the replicating transistor and the buffer output signal to provide a gate signal to the source follower output transistor. A cross current feedback circuit regulates the quiescent current flow through the output transistors by adjusting the gate signal provided to the upper, source follower output transistor in response to a sensed current flow through the lower output transistor.

Abstract: A transversal filter has more delay elements than adjustable multipliers, and a switching arrangement for supplying each multiplier with the signal from a selected one of a group of the elements. Each element is a member of one of the groups. The outputs of the multipliers are added, and their sum is used to control optimization of the multiplier weights for a given set of switched connections. Successive sets of connections are established to develop sets of optimized weights, until each delay element output has been used. A globally optimized set of connections and weights is then used for processing information.

Abstract: Ghosts in a video signal containing a predetermined reference signal are adaptively cancelled with a sparse transversal filter having fewer multipliers than delay taps. A reference signal identical to the reference signal in the video signal is generated and filtered with the sparse transversal filter. The filtered reference signal and the generated reference signal are subtracted from the part of the video signal containing the predetermined reference signal and the result of the subtraction is compared with a threshold value. The filter multipliers are connected to the delay taps in correspondence to the results of the subtraction which exceed the threshold value, and the multiplier values are adjusted to minimize the result of the subtraction.

Abstract: An adaptive ghost cancellation circuit comprises a transversal filter having a reduced set of multipliers. A predetermined reference signal in the transmitted video signal, and an identical reference signal generated in the ghost cancellation circuit are used to identify optimum active multiplier positions and values during the vertical retrace interval. The optimum filter is then used to cancel any ghosts from the receiver video signal.

Abstract: An analog neural network composed of an array of capacitors for storing weighted electric charges. Electric charges, or voltages, on the capacitors control the impedance (resistance) values of a corresponding plurality of MOSFETs which selectively couple input signals to one input of a summing amplifier. A plurality of semiconductor gating elements (e.g. MOSFETs) selectively couple to the capacitor's weighted analog voltage values received serially over an input line. The weighted voltage on the input line are periodically applied to the proper capacitors in the neural network via the gating elements so as to refresh the weighted electric charges on the capacitors, and at a multiplex rate that maintains the voltages on the capacitors within acceptable tolerance levels.

Abstract: A MOS cascode operational amplifier stage includes a bias circuit in which one of the bias transistors is operated in its triode region while a second MOS transistor in the output cascode stage is saturated, thereby to achieve a maximum signal output amplitude at the cascode amplifier output stage, which is substantially unaffected and/or optimized by variations in processing parameters.

Abstract: A band-pass filter includes an arrangement of individual filter sections and means for weighting and summing the band-pass functions of the filter sections such that the active conjugate pole pairs are arranged in the z plane on a circle concentric to the unit circle and spaced by equal angles with the exception of corrector poles, which are spaced by half-angle increments from the adjacent poles. In the embodiment of the invention described, the filter sections are in the form of digitally controlled switched capacitor filters.

Abstract: A chroma-key circuit is described for use in alternately selecting one of two TV camera outputs to provide a composite picture, wherein the selection is controlled by detecting changes between a background color and an object color sensed by one of the two cameras. Keying is accomplished digitally by comparing the phase of the chrominance signal from the one camera with the phase of a reference signal, and by switching the circuitry to transmit the signal from the one camera only when the chrominance and reference signals are out of synchronization.