Abstract: The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode.

Abstract: According to the present invention, when faulty data bits in a cache memory are not repairable through conventional repair means such as row/column redundancy, the faulty bits are made inaccessible to the microprocessor by rendering invalid an appropriate line of data in the cache memory containing the faulty data. The present invention employs address detection circuitry which detects when a faulty data address stored in the tag RAM is presented during a microprocessor memory cycle and forces the valid bit for that faulty data to a predetermined logic level. When the valid bit associated with the faulty data is set to the predetermined logic level, the tag RAM generates a signal indicative of a "miss" condition. The "miss condition" is communicated to the microprocessor which must access the requested data from main memory, thus effectively bypassing the faulty data. The address detection circuitry of the invalidation circuitry may be expanded to handle any number of faulty data.

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device.

Abstract: According to the present invention, the data access time of a chip select condition of a synchronized memory integrated circuit device is pipelined so that it approximates the normal access time of data for the device. The response time to the chip enable signal during a deselect condition is immediate and thus is not pipelined. The access time of data due to a chip select condition is pipelined and matched with the normal access time of data propagation so that any access time pushout previously incurred when transitioning the device output signal from a high impedance (disabled) to a low impedance (enabled) state is eliminated. The circuitry of the present invention tri-states the output pin of the synchronized memory device on the initial rising edge of an external clock signal supplied to the device upon a deselect condition. Upon the first cycle of the select condition, when the external clock signal initially rises, an Output Disable Internal signal remains a high logic state.

Abstract: According to the present invention, faulty lines of data of a set associative cache memory containing one or more faulty data bits which are not repairable through conventional repair means such as row/column redundancy, are not updated following a cache miss condition and thereby effectively bypassed. Replacement logic circuitry detects and controls the state of a replacement status bit associated with each line of data of the set associative cache memory to determine if the line of data in the cache should be updated or bypassed. Thus, when replacing a line of data, the replacement logic circuitry detects the address of a faulty line of data in a particular set and avoids updating that faulty line of data in favor of updating another line of data of another set.

Abstract: A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.

Abstract: A safety nut assembly is provided for mounting to the carriage of a backstand apparatus to which a large roll of paper is rotatably mounted. The backstand apparatus includes an inclined screw spindle to which the carriage is threadedly engaged, such that rotation of the screw spindle moves the carriage therealong. The safety nut assembly comprises a mounting portion for secure but removable mounting to the carriage of the backstand. The safety nut assembly further includes a threaded aperture for threadedly engaging the inclined screw spindle. The threaded grooves of the threaded aperture in the safety nut assembly are larger than the threads of the primary weight-bearing bushing in the carriage. Thus, the safety nut assembly will assume a weight-bearing function only upon failure of the primary bushing in the carriage.

Abstract: Bio-oxidative treatment of aqueous waste by means of a partially submerged rotating biological contactor (or RBC) is improved by suffusing the rising submerged quadrant of an RBC with air furnished within the RBC perimeter. Air is distributed along and outward from the rotational axis and is released between discs of the RBC. Some of the air so released is trapped by protrusions on the discs. Rotation of such RBC is accomplished or at least aided by differential buoyancy imparted by such air suffusion and trapping.

Abstract: Gravity flow of liquid in sewer pipes or similar conduits is determined in the absence of a weir, flume, or similar flow-rating device by sensing the depth of the liquid in the pipe, converting such depth to the corresponding rate of flow through the pipe in accordance with a known relationship of depth to flow and without performing any mental computation, and providing a readable indication of instantaneous flow rate, and/or optionally integrating the flow rate over time, recording such flow rate and/or the integrated flow, printing out one or the other, or both, etc. Apparatus for doing so includes a pressure sensor, a depth-to-flow converter, and usually a separate indicator/recorder. Unlike systems utilizing flumes or weirs, this apparatus and this method can accommodate sludge deposited in a pipe or other conduit to be monitored.

Abstract: Flow velocity of a liquid stream in a sewer or water pipe or conduit is determined by injecting electrically conductive fluid transversely of the flow and measuring the time for the increased conductivity to be sensed at a given location downstream from the injection location. In conjunction with measurement of flow depth as by bubbling a gaseous fluid into the liquid stream and determining the back pressure applied thereto by the overlying liquid, highly accurate monitoring of flow rate and volume becomes feasible.

Abstract: A probe adapted to fit an open end of a sewer or water pipe or conduit is provided with jets at an upstream portion and sensors at a downstream portion for detecting jetted fluid. In conjunction with timing means and with means for determining flow depth, such as a bubbler device, such probe provides highly accurate calculation of flow velocity by a rate computer. The velocity multiplied by the output of means for converting the flow depth to cross-sectional area of flowing liquid, provides the instantaneous flow, which integrated over time gives total flow.

Abstract: Liquid flow in an open channel is monitored by sensing pressure of overlying liquid as depth thereof, transmitting changes in the sensed depth to means for characterizing depth as flow, and indicating the liquid flow so characterized. The pressure sensing and the transmittal of changes in sensed depth are accomplished pneumatically, via a bubbler tube and bellows plus self-balancing cam-and-valve means for controlling rotation of an air motor.

Abstract: A probe adapted to fit an open end of a sewer or water conduit is provided with jets at an upstream portion and sensors at a downstream portion for detecting jetted fluid. In conjunction with timing means and with means for determining flow depth, such as a bubbler device, highly accurate monitoring of flow rate and volume becomes feasible.

Abstract: Liquid samples of like composition and like or unlike volume are collected simultaneously. Liquid is withdrawn continuously from a body of liquid to be sampled. The withdrawn liquid is passed continuously into and fills a confining region having multiple outlets. Streams of liquid from the respective outlets are diverted intermittently for sample collection and otherwise are returned to the source body of liquid or to waste. The multiple-outlet confining region is embodied in a plenum chamber, and individual diverter chambers are provided for the streams of liquid from the plenum chamber, together with means for effecting the diversion.