Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Abstract: In a computer system, a processing unit generates a read request and sends it to a cache. If data for the read request is not in the cache, the cache forwards the request to a bus interface unit. If the forwarded request does not fall within the address range of any bus read transaction stored in the bus interface unit, the bus interface unit stores a new bus read transaction corresponding to the forwarded request and sends an identifier for the new transaction to the processing unit. In one preferred embodiment, if the forwarded request falls within the address range of one of the bus read transactions stored in the bus interface unit, the bus interface unit discards the forwarded request and sends an identifier for the one transaction to the processing unit. Additionally, a method of processing read requests is provided. A read request is stored in a buffer and sent to a cache.