Abstract: A mask structure and photolithographic method using the same for obtaining shorter and thinner line or feature lengths for optimizing power consumption and performance in semiconductor devices. According to a first aspect, a method for enabling trimming of semiconductor linewidth dimensions implements an extra dose trim mask. The lithographic method using the extra dose trim mask to make small adjustments to patterned linewidth exposures for enhanced CD control may be used to trim or adjust whole or a plurality of regions of a lithographic exposure. There is additionally provided a structure and method of creating a lithographic dual exposure mask having one or more regions comprising one or more partial energy absorptive layers such that, when subject to a blanket dose, enable smaller image size adjustments in those regions.

Abstract: The present invention relates to determining the location of a defect source which results in a localized elevation on the surface topography of a substrate such as, for example, a silicon wafer. The wafer is placed on a chuck of a semiconductor process tool such as, for example, a photolithographic tool. The upper surface of the wafer is processed by the photolithographic tool to obtain topography measurements. The topography measurements are analyzed to detect the presence of the localized elevation on the upper surface of the wafer. Once the presence of the localized elevation is detected, calculations are performed using the topography measurements to determine whether the source of the localized elevation results from the chuck.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: The present invention relates to determining the location of a defect source which results in a localized elevation on the surface topography of a substrate such as, for example, a silicon wafer. The wafer is placed on a chuck of a semiconductor process tool such as, for example, a photolithographic tool. The upper surface of the wafer is processed by the photolithographic tool to obtain topography measurements. The topography measurements are analyzed to detect the presence of the localized elevation on the upper surface of the wafer. Once the presence of the localized elevation is detected, calculations are performed using the topography measurements to determine whether the source of the localized elevation results from the chuck.

Abstract: A system and method of monitoring and predicting tool overlay settings comprise generating current lot information, generating historical data, categorizing (binning) the historical data into discrete exposure field size ranges, and predicting current lot tool overlay settings based on the current lot information and historical data. The method monitors the overlay errors during each lot pass through each lithographic process operation. Moreover, the method uses a feedback sorting criteria to monitor the tool overlay settings. Furthermore, the current lot information comprises lithographic field dimensions, wherein the lithographic field optics distortion data is derived from the current lithographic process tool. Additionally, the historical data comprises same-bin lithographic field size dimensions of previous lots, which statistically means the data is derived from the same (or similar) bin of like lots, on the current lithographic process tool.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: A method and system embodying the present invention for predicting systematic overlay affects in semiconductor lithography. This method is a feed-forward method, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot. Instead of using population averaging, which ignores process variability, it acknowledges the variability and uses prior measurements to advantage. The principle, backed by production data, is that “systematic” overlay errors are just that: Image placement errors which persist through processing and will be predictable through time and processing.

Abstract: A system and method of monitoring and predicting tool overlay settings comprise generating current lot information, generating historical data, categorizing (binning) the historical data into discrete exposure field size ranges, and predicting current lot tool overlay settings based on the current lot information and historical data. The method monitors the overlay errors during each lot pass through each lithographic process operation. Moreover, the method uses a feedback sorting criteria to monitor the tool overlay settings. Furthermore, the current lot information comprises lithographic field dimensions, wherein the lithographic field optics distortion data is derived from the current lithographic process tool. Additionally, the historical data comprises same-bin lithographic field size dimensions of previous lots, which statistically means the data is derived from the same (or similar) bin of like lots, on the current lithographic process tool.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: A method and an arrangement for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value.

Abstract: A method and system embodying the present invention for predicting systematic overlay affects in semiconductor lithography. This method is a feed-forward method, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot. Instead of using population averaging, which ignores process variability, it acknowledges the variability and uses prior measurements to advantage. The principle, backed by production data, is that “systematic” overlay errors are just that: Image placement errors which persist through processing and will be predictable through time and processing.

Abstract: A method for the control of wafer surface temperatures during post exposure bake on hot plates of wafers which carry integrated circuits. Also disclosed is a method of maximizing image size uniformity for integrated circuits through the zonal control of temperatures of hot plates during post exposure bake processes for effectively modulating the wafer surface temperatures. Images within a semiconductor wafer integrated circuit line pattern are repeated to process a wafer through the photolithographic patterning process, including post exposure baking, to measure the image linewidths and compare these with an experimentally derived correlation chart; for instance, PEB temperature vs. linewidth for a given or specified photomasking process.

Abstract: An alignment mark includes aspects of alignment marks used for two or more photolithography systems. Because the new mark includes the features specified for each system it can be read by the detectors of both systems. Since each photolithography system is substantially insensitive to the presence of the aspect used by the other system precision alignment can be achieved by each system.

Abstract: A method and apparatus according to the present invention achieves improved lithographic printing of semiconductor wafers. An optimum tilt for projection optics in a lithography tool relative to a wafer in a direction perpendicular to a scanning direction is characterized for each of a plurality of wafer technologies and levels. The corresponding optimum tilt is retrieved from a database to adjust the lithography tool accordingly, depending upon what technology and level is being processed.

Abstract: A method for the control of wafer surface temperatures during post exposure bake on hot plates of wafers which carry integrated circuits. Also disclosed is a method of maximizing image size uniformity for integrated circuits through the zonal control of temperatures of hot plates during post exposure bake processes for effectively modulating the wafer surface temperatures. Images within a semiconductor wafer integrated circuit line pattern are repeated to process a wafer through the photolithographic patterning process, including post exposure baking, to measure the image linewidths and compare these with an experimentally derived correlation chart; for instance, PEB temperature vs. linewidth for a given or specified photomasking process.

Abstract: A method for the control of wafer surface temperatures during post exposure bake on hot plates of wafers which carry integrated circuits. Also disclosed is a method of maximizing image size uniformity for integrated circuits through the zonal control of temperatures of hot plates during post exposure bake processes for effectively modulating the wafer surface temperatures. Images within a semiconductor wafer integrated circuit line pattern are repeated to process a wafer through the photolithographic patterning process, including post exposure baking, to measure the image linewidths and compare these with an experimentally derived correlation chart; for instance, PEB temperature vs. linewidth for a given or specified photomasking process.

Abstract: An arrangement and method for controlling individual zones of a hot plate which is employed in a post exposure bake step of wafers in the fabrication of semi-conductor devices incorporating photolithographic processes using chemically amplified resist systems. Provided is an in situ temperature-controllable hot plate which includes temperature-controllable surface zones for supporting a standard single wafer, and having loading means which orient the wafer on the hot plate. The hot plate may be segmented into an array of individually controllable heating zones, while mounted above the hot plate is a thermal detection array, such as an infrared(IR) camera or pyroelectric or pyrometric detector which functions to detect and scrutinize the wafer surface temperature with regard to specific locations dispersed across the hot plate surface. This particular data is mapped into the hot plate zones, and the mapped data transmitted into a servo for zonal hot plate adjustment and temperature control.

Abstract: A structure and method for removing and recovering an anodically bonded glass device from a substrate using a metal interlayer interposed between the glass and the substrate is provided. As used in semiconductor mask fabrication, the structure comprises a silicon wafer substrate coated with a membrane on which a metal interlayer is disposed. The metal interlayer and a glass device are anodically bonded together. Recovery of the glass device is accomplished by chemically and mechanically removing the wafer and its membrane from the metal interlayer. The membrane is preferably removed using reactive ion etching to which the metal interlayer is resistant. The metal interlayer is then removed from the glass device using a highly corrosive chemical solution. The recovered glass device may then be reused.