Patents by Inventor Charles-Alix Manier

Charles-Alix Manier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210018687
    Abstract: Disclosed herein is an optical system, comprising a first optical component, featuring a first waveguide and a recess which passes at least partially through the first optical component from a front side to a back side, a second optical component, arranged in the recess of the first optical component, and a second waveguide optically coupled with the first waveguide, and a carrier substrate. The first optical component including a first marking set with a defined position/orientation relative to the first waveguide, the second optical component including a second marking set with a defined position/orientation relative to the second waveguide, and based on a relative position/orientation of the first and second marking sets, determine whether the first and the second optical components are aligned in a reference plane that is parallel to a surface of the carrier substrate, such that the first and the second waveguide are optically coupled.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 21, 2021
    Inventors: Hans-Hermann Oppermann, Tolga Tekin, Charles-Alix Manier
  • Publication number: 20210018679
    Abstract: Disclosed is a system for and a method of manufacturing of an optical system, including a first optical component, comprising a first waveguide and a carrier substrate, wherein the first optical component is arranged on the carrier substrate. The first optical component comprises a first markup set having a defined position/orientation with respect to the first waveguide, the carrier substrate has a second markup set detectable based on a relative position/orientation of the first and second markup sets when a desired orientation of the first waveguide relative to the carrier substrate is achieved in a reference plane extending parallel to a surface of the carrier substrate.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 21, 2021
    Inventors: Charles-Alix Manier, Hans-Hermann Oppermann, Kai Zoschke, Tolga Tekin
  • Patent number: 10658187
    Abstract: A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 19, 2020
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Hans-Hermann Oppermann, Kai Zoschke, Charles-Alix Manier, Martin Wilke, Tolga Tekin, Robert Gernhardt
  • Publication number: 20190088490
    Abstract: A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 21, 2019
    Inventors: Hans-Hermann Oppermann, Kai Zoschke, Charles-Alix Manier, Martin Wilke, Tolga Tekin, Robert Gernhardt