Abstract: A packaged semiconductor device (100) comprising a semiconductor chip (101) of an area having a first surface (101a) including a plurality of bond pads (102) linearly arrayed, adjacent pads having a first pitch (103) center-to-center; an insulating layer (110) on the first chip surface covering the chip area, the layer having a height (116) and a second surface (110a) parallel to the first surface; the second surface including contact nodes (120) in staggered array, the nodes having the same plurality as the pads, adjacent nodes having a second pitch (121) center-to-center greater than the first pitch; and metal wires through the layer height connecting the pads to respective nodes.

Abstract: A packaged semiconductor device (100) comprising a semiconductor chip (101) of an area having a first surface (101a) including a plurality of bond pads (102) linearly arrayed, adjacent pads having a first pitch (103) center-to-center; an insulating layer (110) on the first chip surface covering the chip area, the layer having a height (116) and a second surface (110a) parallel to the first surface; the second surface including contact nodes (120) in staggered array, the nodes having the same plurality as the pads, adjacent nodes having a second pitch (121) center-to-center greater than the first pitch; and metal wires through the layer height connecting the pads to respective nodes.

Abstract: In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, and spaced apart from, the die, and the first face being opposite the second face. The plurality of separator pedestals are operable to selectively force the die and substrate apart, increasing the stand-off height of the flip chip assembly.

Abstract: The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the invention, a semiconductor device includes an active circuit area surrounded by an inactive area and circumscribed with a bulwark having a crack-deflecting face oriented toward the periphery of the device. Embodiments of the invention are disclosed, in which a semiconductor device, or multiple devices on a wafer, include bulwarks having series of minor arcs with their chords oriented toward the peripheries of the devices. Additional embodiments of the invention described include bulwarks having series of right angles oriented toward the peripheries of the devices. Examples of the invention also include preferred embodiments wherein the bulwarks further comprise series of discrete pickets, parallel bulwarks, and bulwarks in combination with scribe seals.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the die during heating of the solder to a liquescent state, thereby increasing the stand-off height of the die above the substrate. The lifting force is maintained during cooling of the solder to a solid state, thereby forming increased stand-off height solder connections.

Abstract: Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the die during heating of the solder to a liquescent state, thereby increasing the stand-off height of the die above the substrate. The lifting force is maintained during cooling of the solder to a solid state, thereby forming increased stand-off height solder connections.

Abstract: In a method and system for underfilling a gap (140) disposed between a substrate (120) and a die (110), a selective surface (152) of the substrate (120) is treated by a plasma source. A matching surface (154) of the die (110) may be treated by the plasma source. The treating results in a roughening of the selective surface (152) and the matching surface (154). The roughening improves welting of an underfill (150) on the selective surface (152) and the matching surface (154) compared to a non-treated surface. The underfill (150) is dispensed to substantially fill the gap (140) disposed between the selective surface (152) and the matching surface (154) of the die 110. The underfill (150) is substantially contained within the gap (140) by the wetting, which reduces the backflow and the bleed of the underfill (150).

Abstract: In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, and spaced apart from, the die, and the first face being opposite the second face. The plurality of separator pedestals are operable to selectively force the die and substrate apart, increasing the stand-off height of the flip chip assembly.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, and spaced apart from, the die, and the first face being opposite the second face. The plurality of separator pedestals are operable to selectively force the die and substrate apart, increasing the stand-off height of the flip chip assembly.

Abstract: A probe having a built-in reference plane for use with TDR testing includes a conductive sheet member such as a wire mesh which is attached to a ground input of a TDR system. The conductive sheet is located proximate the tip of the test probe and extends radially from an axis of the test probe thereby providing its own reference ground plane.

Abstract: A probe having a built-in reference plane for use with TDR testing is disclosed. The probe includes a conductive sheet member such as a wire mesh which is attached to a ground input of a TDR system. The conductive sheet is located proximate the tip of the test probe and extends radially from an axis of the test probe thereby providing its own reference ground plane.