Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

Abstract: An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes.

Abstract: An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes.

Abstract: A process of programming or reprogramming a reprogrammable onboard memory (5) comprises programming or reprogramming the onboard memory of several modules (M0, M1) in parallel through a multiple access bus (6) to which the modules are connected. In the case of blank flash memories, a process downloads code through the multiple access bus (6) and executes the code, eliminating all external constraints (such as frequency, binary throughput). The process is more particularly intended to apply to onboard flash type memories.

Abstract: The invention relates to a process for programming or reprogramming a reprogrammable onboard memory (5), characterised in that it consists of programming or reprogramming the onboard memory of several modules (M0, M1 . . . ) in parallel through a multiple access bus (6) to which the said modules are connected. In the case of blank flash memories, the invention also defines a process used to download code through the multiple access bus and to execute it, eliminating all external constraints (frequency, binary throughput).