Abstract: A system and method for event matching by analysis of text characteristics are presented. A document collection comprising documents is acquired. One or more document subsets of the document collection each comprising one or more documents potentially describing identical events are identified based on certain structured metadata fields of the documents. Salient text features are extracted from the documents in the document collection. An event similarity score for pairs of documents in the document collection is generated by comparing the text features extracted from the documents. A common event document list comprising sets of documents in the document collection whose event similarity scores with each other are above a similarity threshold is generated.

Abstract: Provided are an apparatus, video processing unit, and method for clustering events in a content addressable memory. An event is received including at least one parameter value and a timestamp. A determination is made as to whether there is a valid entry in the memory having at least one parameter value within a predefined range of values of the at least one parameter value in the event. In response to a determination that there is the valid entry, writing the at least one parameter value and the timestamp in the event to the valid entry.

Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.

Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.

Abstract: A system and method for event matching by analysis of text characteristics are presented. A document collection comprising documents is acquired. One or more document subsets of the document collection each comprising one or more documents potentially describing identical events are identified based on certain structured metadata fields of the documents. Salient text features are extracted from the documents in the document collection. An event similarity score for pairs of documents in the document collection is generated by comparing the text features extracted from the documents. A common event document list comprising sets of documents in the document collection whose event similarity scores with each other are above a similarity threshold is generated.

Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.

Abstract: Systems, apparatuses and methods may provide a hybrid compression scheme to store synaptic weights in neuromorphic cores. The hybrid compression scheme utilizes a run-length encoding (RLE) compression approach, a dictionary-based encode compression scheme, and a compressionless encoding scheme to store the weights for valid synaptic connections in a synaptic weight memory.

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.

Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.

Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract: Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.

Abstract: Some embodiments include apparatus and methods using a first ring oscillator, a second ring oscillator, and circuit coupled to the first and second ring oscillators. The first ring oscillator includes a first memory cell and a first plurality of stages coupled to the first memory cell. The second ring oscillator includes a second memory cell and a second plurality of stages coupled to the second memory cell. The circuit includes a first input node coupled to an output node of the first ring oscillator and a second input node coupled to an output node of the second ring oscillator. In one of such embodiments, the circuit can operate to generate identification information to authenticate the apparatus.

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.