Abstract: An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.

Abstract: A level shifting circuit operating at low power with minimal signal delays. The circuit employs high capacitance diodes to shift signals from a first signal level to a second higher or lower signal level. The capacitance is obtained by either providing a discrete capacitor shunt across the diode or by using diode connected transistors. Diode connected transistors are biased to provide the necessary capacitance. A pair of high capacitance diode level shifters is used as a differential pair level shifter by connecting the reference resistors to a common reference potential.