Abstract: A first photonic integrated circuit (PIC) comprises a first optical element optically coupled to a first coupling region at an edge of the first PIC. A second PIC is formed in part from a multilayer structure comprising a bottom layer, a top layer comprising a first material with a first index of refraction, and a middle layer comprising a second material with a second lower index of refraction and having a first thickness between the bottom and top layers. The second PIC comprises a plurality of vertical alignment pedestals comprising a portion of the middle layer having the first thickness and attached to at least a portion of the bottom layer, a plurality of thinned regions, and a second optical element optically coupled to a second coupling region at an edge of the second PIC. Two or more of the vertical alignment pedestals are adhered to the first PIC.

Abstract: One or more photonic structures are formed within one or more layers over a surface of a substrate, and multiple trenches are formed through the one or more layers housing devices coupled to one or more of the photonic structures. The trenches may include: a first trench that has a bottom surface within the substrate that has a first surface topology characterized by a first surface roughness at a first depth within the substrate relative to the surface of the substrate, and a second trench that has a bottom surface within the substrate that has a second surface topology characterized by a second surface roughness at a second depth within the substrate relative to the surface of the substrate. The first surface roughness may be greater than the second surface roughness, and the second depth may be greater than the first depth.

Abstract: Aspects of the subject disclosure may include, for example, a process that provides a semiconductor substrate and forms repeating, conductive patterns configured for coupling to active circuitry. Each pattern comprises a group of thermally conductive layers, wherein the group of thermally layers is thermally coupled to a thermal source generated by the active circuitry. Thermally conductive vias interconnect the group of thermally conductive layers, wherein a combination of the vias and the group of thermally conductive layers is configured to transfer heat from the thermal source with a desired directionality. The first repeating patterns are thermally coupled to each other to combine the desired directionality of each of the patterns, wherein the combination results in a distributed directionality of the heat from the thermal source thereby reducing a localized concentration of the heat. Other embodiments are disclosed.

Abstract: An article comprises: one or more sets of lower index contrast layers, each comprising at least two materials having different indices of refraction, and configured to provide optical confinement based at least in part on a first numerical difference between the two indices of refraction; and one or more sets of higher index contrast layers, each comprising at least two materials having different indices of refraction, and configured to provide optical confinement based at least in part on a second numerical difference; and at least one optical coupler configured to optically couple a first of the one or more sets of lower index contrast layers to a first of the one or more sets of higher index contrast layers. The first numerical difference is smaller than the second numerical difference.

Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.

Abstract: Aspects of the subject disclosure may include, for example, a process that provides a semiconductor substrate and forms repeating, conductive patterns configured for coupling to active circuitry. Each pattern comprises a group of thermally conductive layers, wherein the group of thermally layers is thermally coupled to a thermal source generated by the active circuitry. Thermally conductive vias interconnect the group of thermally conductive layers, wherein a combination of the vias and the group of thermally conductive layers is configured to transfer heat from the thermal source with a desired directionality. The first repeating patterns are thermally coupled to each other to combine the desired directionality of each of the patterns, wherein the combination results in a distributed directionality of the heat from the thermal source thereby reducing a localized concentration of the heat. Other embodiments are disclosed.

Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.

Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.

Abstract: A carrier depletion-based Silicon Photonic (SiP) modulator using capacitive coupling includes a high-k dielectric material in or on slabs, between a rib. A capacitance (Ck) of the high-k dielectric material is larger than a capacitance (Cpn) of the rib, thereby reducing the high frequency impedance and improving bandwidth of the modulator. A modulator includes a first electrode; a first slab connected to the first electrode at a first end; a rib connected to the first slab at a second end of the first slab; a second slab connected to the rib at a first end; a second electrode connected to the second slab at a second end of the second slab; and a high-k dielectric material disposed in or on a portion of each of the first slab and the second slab, thereby enabling capacitive coupling.

Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.

Abstract: A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elem

Abstract: In one embodiment, an electro-optical modulator includes a waveguide having a first major surface and a second major surface opposite the first major surface. A cavity is disposed in the waveguide. Multiple quantum wells are disposed in the cavity.

Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.

Abstract: A silicon-on-insulator (SOI) substrate includes a silicon dioxide layer and a silicon layer. A detection region receives a detected optical mode coupled to an incident optical mode defined by an optical waveguide in the silicon layer. The detection region consists essentially of an intrinsic semiconductor material with a spacing structure surrounding at least a portion of the detection region, which comprises p-type, n-type doped semiconductor regions adjacent to first, second portions, respectively, of the detection region. A dielectric layer is deposited over at least a portion of the spacing structure. The silicon layer is located between the dielectric layer and the silicon dioxide layer. First, second metal contact structures are formed within trenches in the dielectric layer electrically coupling to the p-type, n-type doped semiconductor regions, respectively, without contacting any of the intrinsic semiconductor material of the detection region.

Abstract: A method of Silicon Selective Epitaxial Growth (SEG) applied to a Silicon on Insulator (SOI) wafer to provide a first region of customized thickness includes with the SOI wafer having a standard thickness, applying a hard mask to a plurality of regions of the SOI wafer including the first region; applying photo-lithography protection to cover the hard mask in all of the plurality of regions except the first region; removing the hard mask in the first region; and performing Silicon SEG in the first region to provide the customized thickness in the first region, wherein the customized thickness is greater than the standard thickness.

Abstract: At least a portion of an integrated circuit wafer includes at least one layer in which two or more waveguides are formed. A cavity is formed in the integrated circuit wafer. At least one die, comprising a photonic integrated circuit, has: at least one edge on which there are two or more optical mode defining structures in proximity to respective optical mode defining structures on at least one surface of the cavity, a bottom surface secured to a bottom surface of the cavity, and a top surface on which there is at least one metal contact.

Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.

Abstract: A carrier depletion-based Silicon Photonic (SiP) modulator using capacitive coupling includes a high-k dielectric material in or on slabs, between a rib. A capacitance (Ck) of the high-k dielectric material is larger than a capacitance (Cpn) of the rib, thereby reducing the high frequency impedance and improving bandwidth of the modulator. A modulator includes a first electrode; a first slab connected to the first electrode at a first end; a rib connected to the first slab at a second end of the first slab; a second slab connected to the rib at a first end; a second electrode connected to the second slab at a second end of the second slab; and a high-k dielectric material disposed in or on a portion of each of the first slab and the second slab, thereby enabling capacitive coupling.

Abstract: In one embodiment, an electro-optical modulator includes a waveguide having a first major surface and a second major surface opposite the first major surface. A cavity is disposed in the waveguide. Multiple quantum wells are disposed in the cavity.

Abstract: At least a portion of an integrated circuit wafer includes at least one layer in which two or more waveguides are formed. A cavity is formed in the integrated circuit wafer. At least one die, comprising a photonic integrated circuit, has: at least one edge on which there are two or more optical mode defining structures in proximity to respective optical mode defining structures on at least one surface of the cavity, a bottom surface secured to a bottom surface of the cavity, and a top surface on which there is at least one metal contact.