Abstract: A system and method for progressively identifying and configuring the nodes of a network having an unknown or partially unknown topology are presented. A special all-node address indicator is designated for insertion in a packet to be sent from a given node with known node address to a next adjacent node with unknown node address. Each node contains a port control register for each port of the node which when set instructs the node to insert the all-node address indicator into a packet to be forwarded to a next adjacent node in the network with unknown node address. The port control registers are remotely selectively set by one or more managing nodes of the network. Race condition is avoided by provision of a set count register associated with an address node register and managing node address register within each node of the network.

Abstract: A system of supporting differential signalling circuitry in an enhanced PCI bus within a data processing system is disclosed The enhanced PCI bus comprises a plurality of differential signal conductor pairs. A system and method in accordance with the present invention comprises a system for providing each of the plurality of differential signal pairs over a first line and a second line, the first line having a front end and a back end, the second line having a front end and a back end. The system and method includes a differential driver for driving the first line and the second line with a small voltage change of equal amounts in opposite direction to change logic states, a receiver for sensing a voltage change between the first line and the second line and a termination network coupled to the first line and second line for terminating the first line and the second line.

Abstract: An enhanced PCI bus architecture utilizing differential signaling is supported by an adapter slot connector providing differential signaling pins and a make-before-break connection between bus conductors and dummy loads for each bus conductor, enabling higher frequency and higher bandwidth operation. The dummy loads simulate the signal load of an adapter inserted into the slot. The PCI bus conductors are automatically disconnected from the dummy loads and connected to the adapter pins when an adapter is inserted into the slot. A balanced load bus is thus provided regardless of whether adapter slots are populated or empty.