Abstract: A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths, lightly doped source/drain, and shallow junction depths was achieved. The method for fabricating the FET includes a doped pad oxide layer that functions as both an etch stop layer and a diffusion source for the lightly doped drain. The doped pad oxide prevents the substrate from being etched when a channel opening for the gate electrode is etched in a source/drain polysilicon layer. The sub-quarter micrometer channel length was achieved by reducing the channel opening by sidewall spacer techniques. The shallow source/drain junctions out diffused from the polysilicon are about 0.10 to 0.15 um depth, and the lightly doped source/drain junctions are about 0.05 to 0.08 um depth.