Patents by Inventor Charles C. Kuo
Charles C. Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092947Abstract: The present disclosure relates to supported catalyst systems for olefin polymerization, catalyst system precursors, methods of producing the precursors and catalyst systems and polyolefins formed from the catalyst systems.Type: ApplicationFiled: November 17, 2021Publication date: March 21, 2024Inventors: Lubin LUO, Francis C. RIX, Kevin A. Stevens, Chi-l KUO, Xiaodan ZHANG, Jacqueline A. LOVELL, Charles J. HARLAN, Xuan YE, Brian R. BERG
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Publication number: 20240006499Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Cheng-Ying Huang, Kai Loon Cheong, Pooja Nath, Susmita Ghose, Rambert Nahm, Natalie Briggs, Charles C. Kuo, Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Jack T. Kavalieros, Thoe Michaelos, David Kohen
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Patent number: 11812600Abstract: An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.Type: GrantFiled: June 25, 2019Date of Patent: November 7, 2023Assignee: Intel CorporationInventors: Seung Hoon Sung, Charles C. Kuo, Abhishek A. Sharma, Van H. Le, Jack Kavalieros
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Publication number: 20230197728Abstract: An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Nicole K. Thomas, Eric Mattson, Sudarat Lee, Sarah Atanasov, Christopher J. Jezewski, Charles Mokhtarzadeh, Thoe Michaelos, I-Cheng Tung, Charles C. Kuo, Scott B. Clendenning, Matthew V. Metz
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Publication number: 20230089395Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: INTEL CORPORATIONInventors: Benjamin Orr, Nicholas A. Thomson, Ayan Kar, Nathan D. Jack, Kalyan C. Kolluru, Patrick Morrow, Cheng-Ying Huang, Charles C. Kuo
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Publication number: 20230087444Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: INTEL CORPORATIONInventors: Nicholas A. Thomson, Ayan Kar, Benjamin Orr, Kalyan C. Kolluru, Nathan D. Jack, Patrick Morrow, Cheng-Ying Huang, Charles C. Kuo
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Publication number: 20230088578Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction paths.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: INTEL CORPORATIONInventors: Nicholas A. Thomson, Ayan Kar, Benjamin Orr, Kalyan C. Kolluru, Nathan D. Jack, Patrick Morrow, Cheng-Ying Huang, Charles C. Kuo
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Publication number: 20220199609Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Urusa ALAAN, Abhishek A. SHARMA, Charles C. KUO, Benjamin ORR, Nicholas THOMSON, Ayan KAR, Arnab SEN GUPTA, Kaan OGUZ, Brian S. DOYLE, Prashant MAJHI, Van H. LE, Elijah V. KARPOV
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Publication number: 20220199801Abstract: Embodiments disclosed herein include a semiconductor devices with back end of line (BEOL) transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a BEOL stack over the semiconductor substrate. In an embodiment, a field effect transistor (FET) is embedded in the BEOL stack. In an embodiment, the FET comprises a channel, a gate dielectric over the channel, where the gate dielectric is single crystalline, a gate electrode over the gate dielectric, and a source electrode and a drain electrode passing through the gate dielectric to contact the channel.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Prashant MAJHI, Abhishek A. SHARMA, Charles C. KUO, Brian S. DOYLE, Urusa ALAAN, Van H. LE, Elijah V. KARPOV, Kaan OGUZ, Arnab SEN GUPTA
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Publication number: 20220199839Abstract: Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Arnab SEN GUPTA, Urusa ALAAN, Justin WEBER, Charles C. KUO, Yu-Jin CHEN, Kaan OGUZ, Matthew V. METZ, Abhishek A. SHARMA, Prashant MAJHI, Brian S. DOYLE, Van H. LE
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Patent number: 11295884Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.Type: GrantFiled: September 30, 2016Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Charles C. Kuo, Mark L. Doczy
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Patent number: 11264428Abstract: An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction above a substrate. A memory element is coupled between the bottom electrode and the conductive line, the memory element comprising a phase change material layer that is self-aligned with the conductive line.Type: GrantFiled: September 29, 2017Date of Patent: March 1, 2022Assignee: Intel CorporationInventor: Charles C. Kuo
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Publication number: 20210296040Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.Type: ApplicationFiled: September 30, 2016Publication date: September 23, 2021Applicant: INTEL CORPORATIONInventors: KAAN OGUZ, KEVIN P. O'BRIEN, BRIAN S. DOYLE, CHARLES C. KUO, MARK L. DOCZY
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Patent number: 11031545Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.Type: GrantFiled: September 30, 2016Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz
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Patent number: 10950660Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack and a fixed magnetic stack separated by a dielectric tunneling layer. The free magnetic stack includes an uppermost magnetic layer that is at least partially covered by a cap layer. The cap layer is at least partially covered by a protective layer containing at least one of: ruthenium (Ru); cobalt/iron/boron (CoFeB); molybdenum (Mo); cobalt (Co); tungsten (W); or platinum (Pt). The protective layer is at least partially covered by a cap metal layer which may form a portion of MTJ electrode. The protective layer minimizes the occurrence of physical and/or chemical attack of the cap layer by the materials used in the cap metal layer, beneficially improving the interface anisotropy of the MTJ free magnetic layer.Type: GrantFiled: September 29, 2016Date of Patent: March 16, 2021Assignee: Intel CorporationInventors: Kaan Oguz, Kevin P. OBrien, Brian S. Doyle, Charles C. Kuo, Mark L. Doczy
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Publication number: 20200411528Abstract: An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Applicant: Intel CorporationInventors: Seung Hoon Sung, Charles C. Kuo, Abhishek A. Sharma, Van H. Le, Jack Kavalieros
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Patent number: 10832847Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.Type: GrantFiled: June 26, 2015Date of Patent: November 10, 2020Assignee: Intel CorporationInventors: Brian S. Doyle, Kaan Oguz, Kevin P. O'Brien, David L. Kencke, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, Robert S. Chau
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Patent number: 10832749Abstract: An embodiment includes an apparatus including: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, including a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.Type: GrantFiled: June 26, 2015Date of Patent: November 10, 2020Assignee: Intel CorporationInventors: Charles C. Kuo, Justin S. Brockman, Juan G. Alzate Vinasco, Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Satyarth Suri, Robert S. Chau
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Patent number: 10707409Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.Type: GrantFiled: January 29, 2018Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, David L. Kencke, Satyarth Suri, Robert S. Chau
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Publication number: 20200161370Abstract: An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction above a substrate. A memory element is coupled between the bottom electrode and the conductive line, the memory element comprising a phase change material layer that is self-aligned with the conductive line.Type: ApplicationFiled: September 29, 2017Publication date: May 21, 2020Inventor: Charles C. KUO