Abstract: A DRAM memory controller for a printer having a single host CPU and a bitmap memory. The CPU initiates data transfers synchronously to a system clock for filling the bitmap memory, and a DMA controller initiates data transfers asynchronously to the system clock for transferring data from the bitmap memory to a print engine. The controller includes a first sequencer for controlling synchronous data transfers initiated by the host CPU, a second sequencer for controlling asynchronous data transfers initiated by the DMA controller, a refresh request generator for generating a refresh request signal which is asynchronous to the system clock, and a third sequencer for controlling memory refresh and for controlling arbtitration betwween the first, second, and third sequencers. Also provided is a method of transferring data between a bitmap memory and a print fifo in a printer.