Abstract: A packaging machine for packaging a product. The machine has a frame for supporting the product and a source of packaging material for supplying packaging material into a position to be engaged by and at least partially surround the product. At least one upper sealing assembly is adapted to move between an actuated position and a non-actuated position. The upper sealing assembly comprises at least one sealing element for forming a seal along adjacent edges of the packaging material. At least one lower sealing assembly is adapted for cooperating engagement with the upper sealing assembly in its actuated position. The at least one upper and lower sealing assemblies are positioned for clamping engagement of the packaging material therebetween for forming the seal when the upper sealing assembly is moved to its actuated position in engagement with the lower sealing assembly.

Abstract: A packaging machine for packaging a product. The machine has a frame for supporting the product and a source of packaging material for supplying packaging material into a position to be engaged by and at least partially surround the product. At least one upper sealing assembly is adapted to move between an actuated position and a non-actuated position. The upper sealing assembly comprises at least one sealing element for forming a seal along adjacent edges of the packaging material. At least one lower sealing assembly is adapted for cooperating engagement with the upper sealing assembly in its actuated position. The at least one upper and lower sealing assemblies are positioned for clamping engagement of the packaging material therebetween for forming the seal when the upper sealing assembly is moved to its actuated position in engagement with the lower sealing assembly.

Abstract: A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.

Abstract: A packaging machine for packaging a product. The machine has a frame for supporting the product and a source of packaging material for supplying packaging material into a position to be engaged by and at least partially surround the product. At least one upper sealing assembly is adapted to move between an actuated position and a non-actuated position. The upper sealing assembly comprises at least one sealing element for forming a seal along adjacent edges of the packaging material. At least one lower sealing assembly is adapted for cooperating engagement with the upper sealing assembly in its actuated position. The at least one upper and lower sealing assemblies are positioned for clamping engagement of the packaging material therebetween for forming the seal when the upper sealing assembly is moved to its actuated position in engagement with the lower sealing assembly.

Abstract: An encoder encodes input data utilizing a binary symmetry-invariant product code including D data bits and P parity bits in each dimension. The encoder includes a half-size data array including K subarrays each having multiple rows of storage for H bits of data, where D is an integer equal to 2×H+1 and K is an integer that is 2 or greater. The encoder is configured to access K rows of data by reading a respective H-bit data word of input data from each of the multiple subarrays and K H-bit data words of duplicate data from across multiple different rows of the subarrays. The encoder further includes at least one register configured to receive the bits read from the half-size data array code and rotate them as needed, at least one row parity generator, and a column parity generator that generates column parities based on row parity.

Abstract: An encoder encodes input data utilizing a binary symmetry-invariant product code. The encoder includes circuitry including a half-size data array including D rows each having storage for H data bits (D=2×H+1). The encoder is configured to access bits of each row of the product code by reading a first H-bit data word from one of the D rows and a second H-bit data word across H different rows of the half-size data array. The encoder additionally includes a register configured to receive the bits of each row of the product code and to rotate the bits to obtain the rows of the product code and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate, based on the row parity, column parities for the parity bits of all rows of the product code.

Abstract: An encoder encodes input data utilizing a binary symmetry-invariant product code. The encoder includes circuitry including a half-size data array including D rows each having storage for H data bits (D=2×H+1). The encoder is configured to access bits of each row of the product code by reading a first H-bit data word from one of the D rows and a second H-bit data word across H different rows of the half-size data array. The encoder additionally includes a register configured to receive the bits of each row of the product code and to rotate the bits to obtain the rows of the product code and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate, based on the row parity, column parities for the parity bits of all rows of the product code.

Abstract: A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.

Abstract: A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.

Abstract: Embodiments for optimizing resource consumption through partial parity information eviction in a storage system of a data storage environment. One or more cooperative Redundant Array of Independent Disks (RAID) parity computations are performed by evicting partial parity data from a RAID controller memory to a storage entity prior to a full stripes worth of data being monotonically written to the storage entity. The storage entity assembles the partial parity data from the one or more cooperative RAID parity computations into a single parity computation valid for the full stripes worth of data, thereby offloading parity computation to the storage entity to more efficiently utilize the RAID controller memory resources.

Abstract: Embodiments for optimizing resource consumption through partial parity information eviction in a storage system of a data storage environment. One or more cooperative Redundant Array of Independent Disks (RAID) parity computations are performed by evicting partial parity data from a RAID controller memory to a storage entity prior to a full stripes worth of data being monotonically written to the storage entity. The storage entity assembles the partial parity data from the one or more cooperative RAID parity computations into a single parity computation valid for the full stripes worth of data, thereby offloading parity computation to the storage entity to more efficiently utilize the RAID controller memory resources.