Abstract: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

Abstract: A method is disclosed to generate and save run time data. The method supplies an embedded device comprising a processor which includes a processor cache, memory, a hardware trace facility comprising a plurality of data buffers, where the embedded device is capable of communicating with one or more host adapter ports. The method generates a trace entry, stores that trace data entry in the processor cache, and then writes the trace data entry to the plurality of data buffers.

Abstract: A method is disclosed to capture data from an embedded device. The method provides an embedded device comprising a processor, memory, and microcode, where the microcode specifies a first fixed address in the memory. The method creates a Registry at the first fixed address, and populates the Registry with a plurality of entries, where each of those entries comprises an address and a data length describing one or more data regions of the memory. The method then performs an LRC check on the Registry, and saves the LRC information to the Registry. If the embedded device fails, the method downloads the Registry, and the data regions described by the Registry for embedded device failure analysis.

Abstract: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

Abstract: An error handling method is provided for processing adapter errors. Rather than executing a disruptive controller hardware reset, an error handling routine provides instructions for a reset operation to be loaded and executed from cache while the SDRAM is in self-refresh mode and therefore unusable.

Abstract: An apparatus, system, and method are provided for identifying fixed memory address errors in source code at build time. The present invention includes a substitution module that substitutes fixed memory address values for hardcoded memory address symbols. The fixed memory address values are substituted according to a mapping between fixed memory address values and hardcoded memory address symbols. A determination module determines size and location information for variables associated with the hardcoded memory address symbols by referencing precompiled object code. A generation module generates one or more conditions and/or memory region conditions that verify memory boundary and/or capacity constraints based on size and location information provided by the determination module. An evaluation module evaluates the conditions and signals an error in response to violation of one of the conditions and/or memory region conditions.