Patents by Inventor Charles Chadwick

Charles Chadwick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954048
    Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Arm Limited
    Inventors: Jason Parker, Yuval Elad, Alexander Donald Charles Chadwick, Andrew Brookfield Swaine, Carlos Garcia-Tobin
  • Patent number: 11853227
    Abstract: There is provided a data processing apparatus and method of data processing. The data processing apparatus comprises storage circuitry to store a hierarchy of page tables comprising an intermediate level page table. Each entry of the intermediate level page table comprises base address information of a next level page table and control information indicating whether an addressing function has been applied to reorder physical storage locations of entries of the next level page table. Address translation circuitry is provided to perform address translations in response to receipt of a virtual address by performing a lookup in a next level page table dependent on the base address information and a page table index from the virtual address. When the control information indicates that the addressing function has been applied, the lookup is performed at a modified storage location generated by applying the addressing function to the page table index.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: December 26, 2023
    Assignee: Arm Limited
    Inventors: Charles Andrew Giefer, Alexander Donald Charles Chadwick
  • Publication number: 20230236987
    Abstract: Apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.
    Type: Application
    Filed: March 8, 2021
    Publication date: July 27, 2023
    Inventors: Yuval ELAD, Richard Roy GRISENTHWAITE, Jason PARKER, Simon John CRASKE, Alexander Donald Charles CHADWICK
  • Publication number: 20230205709
    Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.
    Type: Application
    Filed: April 14, 2021
    Publication date: June 29, 2023
    Inventors: Jason PARKER, Yuval ELAD, Alexander Donald Charles CHADWICK, Andrew Brookfield SWAINE, Carlos GARCIA-TOBIN
  • Publication number: 20230109295
    Abstract: Apparatuses, methods and techniques for controlling memory access in a data processing system are disclosed. The operating data processing system comprises multiple subsystems, each comprising at least one processing element and at least one peripheral device. Memory transaction control circuitry receives memory transaction information of a memory transaction comprising a stream identifier indicative of the issuing peripheral device. A main control register indicates an address of a stream table having multiple entries each comprising an owning subsystem identifier. At least one subsystem control register corresponding to each subsystem of the multiple subsystems stores memory access checking configuration information. On receipt of the memory transaction information an entry of the stream table is selected in dependence on the stream identifier. At least one subsystem control register. corresponding to the subsystem identified by the owning subsystem identifier of the entry is selected.
    Type: Application
    Filed: February 8, 2021
    Publication date: April 6, 2023
    Inventors: Thomas Christopher GROCUTT, Andrew Brookfield SWAINE, Alexander Donald Charles CHADWICK
  • Patent number: 11614985
    Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: March 28, 2023
    Assignee: Arm Limited
    Inventors: Alexander Donald Charles Chadwick, Andrew Brookfield Swaine, Gareth James Evans, Jonathan Curtis Beard
  • Publication number: 20230062127
    Abstract: A knowledge base is collaboratively developed by receiving language input from at least one editor, featurizing it into language elements, extracting predicate sets that are missing predicate arguments, querying editors for input regarding the missing arguments, and updating the knowledge base with suitable predicate arguments and other language elements provided by the editors.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 2, 2023
    Applicant: Live Circle, Inc.
    Inventors: Charles Chadwick, Samuel Brotherton
  • Patent number: 11526541
    Abstract: A knowledge base is collaboratively developed by receiving language input from at least one editor, featurizing it into language elements, extracting predicate sets that are missing predicate arguments, querying editors for input regarding the missing arguments, and updating the knowledge base with suitable predicate arguments and other language elements provided by the editors.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 13, 2022
    Assignee: Live Circle, Inc.
    Inventors: Charles Chadwick, Samuel Brotherton
  • Patent number: 11521173
    Abstract: A computer implemented method for processing products listed in a landscaping project, includes the steps of: collecting and capturing open format raw data of a material list; translating the captured data into text format data; mapping the text format data to generate a matched material list with associated procurement information; generating a smart spreadsheet including an array of smart cells; wherein at least one smart cell corresponds to a particular itemized plant name or landscaping supply to display a content match indicator. When the content match indicator is less than a target value, search for a substitute; forwarding to the client device, the smart spreadsheet for user's selections or modifications to the contents according to user's preference; in response to a user's modifying the content of the smart cell, updating the smart spreadsheet; and displaying a total cost estimate for bidding or for procurement for the landscaping project.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: December 6, 2022
    Assignee: LANDSCAPE HUB, INC.
    Inventors: Charles Chadwick Cooper, Ajay Shriram Jakate, Zachary Samuel Pflederer
  • Publication number: 20220350750
    Abstract: There is provided a data processing apparatus and method of data processing. The data processing apparatus comprises storage circuitry to store a hierarchy of page tables comprising an intermediate level page table. Each entry of the intermediate level page table comprises base address information of a next level page table and control information indicating whether an addressing function has been applied to reorder physical storage locations of entries of the next level page table. Address translation circuitry is provided to perform address translations in response to receipt of a virtual address by performing a lookup in a next level page table dependent on the base address information and a page table index from the virtual address. When the control information indicates that the addressing function has been applied, the lookup is performed at a modified storage location generated by applying the addressing function to the page table index.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Charles Andrew GIEFER, Alexander Donald Charles CHADWICK
  • Publication number: 20220270042
    Abstract: A computer implemented method for processing products listed in a landscaping project, includes the steps of: collecting and capturing open format raw data of a material list; translating the captured data into text format data; mapping the text format data to generate a matched material list with associated procurement information; generating a smart spreadsheet including an array of smart cells; wherein at least one smart cell corresponds to a particular itemized plant name or landscaping supply to display a content match indicator. When the content match indicator is less than a target value, search for a substitute; forwarding to the client device, the smart spreadsheet for user's selections or modifications to the contents according to user's preference; in response to a user's modifying the content of the smart cell, updating the smart spreadsheet; and displaying a total cost estimate for bidding or for procurement for the landscaping project.
    Type: Application
    Filed: November 1, 2021
    Publication date: August 25, 2022
    Inventors: Charles Chadwick Cooper, Ajay Shriram Jakate, Zachary Samuel Pflederer
  • Publication number: 20220197791
    Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Alexander Donald Charles CHADWICK, Andrew Brookfield SWAINE, Gareth James EVANS, Jonathan Curtis BEARD
  • Publication number: 20070040327
    Abstract: Sheet handling mechanism comprising a cassette having a top wall, bottom wall and opposed side walls. The cassette has an open front and is formed with a plurality of shelves to form bins. The bins are positioned on top of each other and are adapted to receive a set of sheets. A feeding mechanism is provided to feed sheets into the bins.
    Type: Application
    Filed: August 4, 2005
    Publication date: February 22, 2007
    Inventors: William Gunther, James Hough, Charles Chadwick
  • Publication number: 20070018374
    Abstract: A sheet handling mechanism having a pair of set removal mechanisms, each set removal mechanism is adapted to remove sets from a cassette. A sensing mechanism senses data on the sets in the cassettes and stores the data. The data on each of the sets being removed from a cassette is sensed. A mechanism for merging a set of one cassette with a set of another cassette is provided to merge the two cassettes together.
    Type: Application
    Filed: July 20, 2005
    Publication date: January 25, 2007
    Inventors: William Gunther, James Hough, Charles Chadwick
  • Patent number: 4927310
    Abstract: Male and female book binding strips are packaged in cassettes and the respective cassettes are stacked in male and female hopper stations. Punched sheets are deposited in a staging station. The components of the book are then assembled in an assembly station. Thus the stack of sheets is fed onto one jaw and one male strip is fed onto that jaw while a female strip is fed onto the opposite jaw superimposed above the first-mentioned jaw. The two jaws are moved toward each other until the stack is loosely held therebetween. Thereupon the jaws are pivoted to vertical position, the stack resting on a base plate attached to one one jaw. The stack is jogged so that the holes in the sheets are aligned with each other and with the holes in the female strip. The male strip is pushed inward toward the stack, the studs fitting through the holes in the sheets and through the female strip.
    Type: Grant
    Filed: February 27, 1989
    Date of Patent: May 22, 1990
    Assignee: VeloBind, Inc.
    Inventors: William H. Abildgaard, Charles Chadwick, Peter Hotkowski, Frank A. Todaro
  • Patent number: 4846616
    Abstract: Male and female book binding strips are packaged in cassettes and the respective cassettes are stacked in male and female hopper stations. Punched sheets are deposited in a staging station. The components of the book are then assembled in an assembly station. Thus the stack of sheets is fed onto one jaw and one male strip is fed onto that jaw while a female strip is fed onto the opposite jaw superimposed above the first-mentioned jaw. The two jaws are moved toward each other until the stack is loosely held therebetween. Thereupon the jaws are pivoted to vertical position, the stack resting on a base plate attached to one jaw. The stack is jogged so that the holes in the sheets are aligned with each other and with the holes in the female strip. The male strip is pushed inward toward the stack, the studs fitting through the holes in the sheets and through the female strip.
    Type: Grant
    Filed: November 2, 1987
    Date of Patent: July 11, 1989
    Assignee: Velo Bind, Inc.
    Inventors: William H. Abildgaard, Charles Chadwick, Peter Hotkowski, Frank A. Todaro