Abstract: A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models.

Abstract: A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models.

Abstract: A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models.

Abstract: A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.

Abstract: The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the case, of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.

Abstract: A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i.e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout.

Abstract: A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments.

Abstract: One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine local critical-area-ratios and optimization potentials for a set of wire-segments. The system can then select a wire segment, and compare its local critical-area-ratio with a global critical-area-ratio. Next, the system can use the result of the comparison to determine a layout optimization. The system can then apply the layout optimization to the wire segment to obtain an improved layout.

Abstract: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

Abstract: A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.

Abstract: One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout such that the PSM-layout is phase-assignable if and only if the phase-conflict graph is bipartite. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. The system can also be used to correct a given set of phase conflicts in a PSM-layout. The system identifies a set of lines in the layout, such that adding space along the set of lines will result in a phase-assignable PSM-layout.

Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Abstract: A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models.

Abstract: A transport and display case for a golf set. The case has a front panel, a pair of side walls, a rear panel, a top and a bottom. The top is transparent so that it allows maximum amount of light into the case to showcase the golf set within. The front panel has two portions: the upper portion is transparent to allow light into the case and allow consumers to view the golf set, while the lower portion is opaque. Both side walls are opaque. The bottom is locked, but can provide easy access by consumers after they purchase the golf set from store. The case is constructed using a cardboard blank with predefined fold lines and cut-out lines. The cut-lines define portions of the case for attaching the transparent covers such as the lid and upper portion. The case can be “sealed” after the golf set is placed in the case. However, to ensure that the golf set, i.e.

Abstract: A fluid filter, which is adapted for separating a less dense fluid floating on a high dense fluid, includes at least a fluid filtering arrangement including a floating wing adapted for floating on the less dense fluid and at least a fluid outlet formed on the floating wing, and a container body, which is extended from the floating wing, having a fluid collecting cavity communicating with the fluid outlet, wherein the fluid outlet is formed at a position above the fluid collecting cavity. Therefore, when a downward force is applied on the floating wing until the fluid outlet is slightly positioned below a surface level of the less dense fluid, the less dense fluid is allowed to flow into the fluid collecting cavity through the fluid outlet by gravity.

Abstract: One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount.

Abstract: A textile fabric for use to make luggage, bags, shoes, etc. includes a fabric base layer having a front side and a back side, and a back coating layer having a bonding side bonded to the back side of the fabric base layer and a back body side. The back coating layer is prepared from TPU (thermoplastic polyurethane), PS (polystyrene), and EVA (ethylene vinyl acetate), and coated on the fabric base layer. Either the fabric base layer or the back coating layer can be exposed to the outside when making luggage, bags, shoes, etc.