Abstract: A liquid crystal display panel includes a substrate, a thin film transistor array, a circuit, and a dummy circuit. One surface of the substrate is divided into a display region and a wiring region. The thin film transistor array is formed on the display region. The circuit and the dummy circuit are formed on the wiring region, the dummy circuit is adjacent to the circuit, and the circuit and the dummy circuit protrude from the substrate.

Abstract: A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.

Abstract: A mother thin film transistor (TFT) array substrate includes an insulating substrate, at least two TFT arrays and printed wirings. The TFT array includes TFTs formed on the insulating substrate. The printed wirings are connected to the TFT arrays. The printed wiring includes a discontinuous metal layer and at least one bridge layer connecting the discontinuous metal layer. The bridge layer is made from corrosion-resistant material.

Abstract: An exemplary liquid crystal display panel includes a substrate and first conductive wires. The first conductive wires are arranged at a surface of the substrate. Each of the first conductive wires includes a plurality of first connecting portions, a plurality of second connecting portions and a conductive portion with a plurality of conductive particles. The conductive portion is sandwiched between the first connecting portions and the second connecting portions, thus electrically connecting the first connecting portions to the second connecting portions. A method for manufacturing the liquid crystal display panel is also provided.

Abstract: A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.

Abstract: A transceiver includes a switching unit configurable for isolating an input of a receiver from an output of a transmitter during a local calibration mode. A known signal present at the output at a first power level during the calibration mode will also be present at the input at a second power level lower than the first power level and will be converted by the quadrature demodulator. A compensation factor is estimated for compensating the receiver section for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal. Remote calibration is implemented using a method for remotely compensating for I-Q imbalance wherein a data packet having a known signal is transmitted to a receiver for conversion by a quadrature demodulator and compensation factors are estimated for compensating for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal.

Abstract: A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances.

Abstract: A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.

Abstract: A receiver, system and method for providing symbol timing recovery that allows for inexpensive and low-complexity synchronization for communication systems. A receiver receives a signal including digital data in the form of packets that is transmitted from a transmitter. The receiver uses information contained in each of the packets to align a phase of the receiver clock with a phase of the transmitter clock. The receiver further controls a sampling device such that the in-phase (I) and quadrature (Q) components are sampled at an optimum sample rate and at an optimum instance of time without requiring a numerically controlled oscillator or voltage controlled oscillator.

Abstract: A transceiver includes a switching unit configurable for isolating an input of a receiver from an output of a transmitter during a local calibration mode. A known signal present at the output at a first power level during the calibration mode will also be present at the input at a second power level lower than the first power level and will be converted by the quadrature demodulator. A compensation factor is estimated for compensating the receiver section for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal. Remote calibration is implemented using a method for remotely compensating for I-Q imbalance wherein a data packet having a known signal is transmitted to a receiver for conversion by a quadrature demodulator and compensation factors are estimated for compensating for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal.

Abstract: A system or method for calibrating an RF transmitter includes inputting a test tone to the RF transmitter. LO leakage calibration is performed on an output of the RF transmitter with the test tone inputted thereto, in order to determine a minimum LO leakage. Thereafter, sideband image calibration is performed on the output of the RF transmitter with the test tone inputted thereto, in order to determine a minimum sideband image. Operational values for the RF transmitter are stored in memory based on the detected minimum LO leakage and the detected minimum sideband image, to be used during a normal operation mode of the RF transmitter.

Abstract: A calibration system for an RF system that includes an RF receiver capable of operating in a normal mode and in a calibration mode. The calibration system includes a phase delay unit provided on at least one of an I channel output and a Q channel output of the RF receiver. The system further includes a phase detector configured to detect a phase difference between the I channel output of the RF receiver and the Q channel output of the RF receiver. The system also includes a calibration control unit configured to provide a digital calibration control signal to the RF receiver based on the phase difference as provided by the phase detector.

Abstract: A transceiver includes a switching unit configurable for isolating an input of a receiver from an output of a transmitter during a local calibration mode. A known signal present at the output at a first power level during the calibration mode will also be present at the input at a second power level lower than the first power level and will be converted by the quadrature demodulator. A compensation factor is estimated for compensating the receiver section for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal. Remote calibration is implemented using a method for remotely compensating for I-Q imbalance wherein a data packet having a known signal is transmitted to a receiver for conversion by a quadrature demodulator and compensation factors are estimated for compensating for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal.

Abstract: An apparatus and method for concealing errors in digital data. An interpolator estimates a value of a sample of digital data from other samples of the digital data. The interpolator has an input for inputting the digital data and an output for outputting the estimated value of the sample of the digital data. A holding unit has an input for selectively receiving the sample of the digital data only when the sample is error free, and an output for outputting the error free sample. The input of the holding unit may be in parallel with the input of the interpolator. A selector selects between outputting the estimated value of the sample of the received digital data from an output of the interpolator and outputting the error free sample of the received digital data from an output of a holding unit based on at least one error indicator.

Abstract: A calibration system for an RF system that includes an RF receiver capable of operating in a normal mode and in a calibration mode. The calibration system includes a phase delay unit provided on at least one of an I channel output and a Q channel output of the RF receiver. The system further includes a phase detector configured to detect a phase difference between the I channel output of the RF receiver and the Q channel output of the RF receiver. The system also includes a calibration control unit configured to provide a digital calibration control signal to the RF receiver based on the phase difference as provided by the phase detector.

Abstract: A system or method for calibrating an RF transmitter includes inputting a test tone to the RF transmitter. LO leakage calibration is performed on an output of the RF transmitter with the test tone inputted thereto, in order to determine a minimum LO leakage. Thereafter, sideband image calibration is performed on the output of the RF transmitter with the test tone inputted thereto, in order to determine a minimum sideband image. Operational values for the RF transmitter are stored in memory based on the detected minimum LO leakage and the detected minimum sideband image, to be used during a normal operation mode of the RF transmitter.

Abstract: The invention monitors a communication channel and estimates its characteristics from time to time, thus providing a dynamic estimate of channel characteristics. Based on the channel characteristics, a control processor calculates a preferred configuration of digital (and optionally, analog) signal processing to best manage the available energy for the present channel characteristics. The selected configuration is then down-loaded into communication modules stored in extra memory during runtime.

Abstract: A transceiver includes a switching unit configurable for isolating an input of a receiver from an output of a transmitter during a local calibration mode. A known signal present at the output at a first power level during the calibration mode will also be present at the input at a second power level lower than the first power level and will be converted by the quadrature demodulator. A compensation factor is estimated for compensating the receiver section for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal. Remote calibration is implemented using a method for remotely compensating for I−Q imbalance wherein a data packet having a known signal is transmitted to a receiver for conversion by a quadrature demodulator and compensation factors are estimated for compensating for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal.

Abstract: An apparatus and method for concealing errors in digital data. An interpolator estimates a value of a sample of digital data from other samples of the digital data. The interpolator has an input for inputting the digital data and an output for outputting the estimated value of the sample of the digital data. A holding unit has an input for selectively receiving the sample of the digital data only when the sample is error free, and an output for outputting the error free sample. The input of the holding unit may be in parallel with the input of the interpolator. A selector selects between outputting the estimated value of the sample of the received digital data from an output of the interpolator and outputting the error free sample of the received digital data from an output of a holding unit based on at least one error indicator.

Abstract: A receiver, system and method for providing symbol timing recovery that allows for inexpensive and low-complexity synchronization for communication systems. A receiver receives a signal including digital data in the form of packets that is transmitted from a transmitter. The receiver uses information contained in each of the packets to align a phase of the receiver clock with a phase of the transmitter clock. The receiver further controls a sampling device such that the in-phase (I) and quadrature (Q) components are sampled at an optimum sample rate and at an optimum instance of time without requiring a numerically controlled oscillator or voltage controlled oscillator.