Abstract: Hardware enforced CPU core protection by identification of digital blocks as instructions or data. A method includes, at a memory controller shim, receiving, from a CPU core, a memory read request. The memory read request comprises an address for a block. The block at the address is requested from a memory. The block is received from the memory. At least one of a decryption key or an authentication key is accessed. At least one of a decryption transformation or an authentication transformation is performed on the block using the decryption key or the authentication key. When the decryption transformation or authentication transformation is deemed valid, a plain text version of the block is returned to the CPU core for consumption. When the decryption transformation or authentication transformation is deemed invalid, the CPU core is prevented from consuming the plain text version of the block.

Abstract: Securely loading digital blocks into memory for consumption by a processor. A method includes, at a memory protection shim, receiving a digital block and a manifest for the digital block. The manifest includes a transformation key for the digital block. The transformation key is configured to be used for at least one of validating the digital block or decrypting the digital block. The manifest is encrypted. The method further includes decrypting the manifest to obtain the transformation keys. The method further includes using the transformation keys to perform at least one of validating or decrypting the digital block. The method further includes retransforming the digital block using a memory protection shim ephemeral key to perform at least one of creating an authentication tag or encrypting the digital block. The method further includes storing the retransformed digital block in memory.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: Hardware enforced CPU core protection by identification of digital blocks as instructions or data. A method includes, at a memory controller shim, receiving, from a CPU core, a memory read request. The memory read request comprises an address for a block. The block at the address is requested from a memory. The block is received from the memory. At least one of a decryption key or an authentication key is accessed. At least one of a decryption transformation or an authentication transformation is performed on the block using the decryption key or the authentication key. When the decryption transformation or authentication transformation is deemed valid, a plain text version of the block is returned to the CPU core for consumption. When the decryption transformation or authentication transformation is deemed invalid, the CPU core is prevented from consuming the plain text version of the block.

Abstract: Hardware enforced CPU core protection by identification of digital blocks as instructions or data. A method includes, at a memory controller shim, receiving, from a CPU core, a memory read request. The memory read request comprises an address for a block. The block at the address is requested from a memory. The block is received from the memory. At least one of a decryption key or an authentication key is accessed. At least one of a decryption transformation or an authentication transformation is performed on the block using the decryption key or the authentication key. When the decryption transformation or authentication transformation is deemed valid, a plain text version of the block is returned to the CPU core for consumption. When the decryption transformation or authentication transformation is deemed invalid, the CPU core is prevented from consuming the plain text version of the block.

Abstract: Systems and methods are presented for passive location of transmitters in which two or more receivers time stamp received signals from target transmitters and the time stamped data for each target signal of interest is isolated to identify a peak power time of arrival for the signal at each transmitter from which differential scan observation values are derived, and for each signal of interest a line of position curve is computed based on the differential scan observation value and corresponding receiver locations, and for each signal of interest an estimated target transmitter location is determined based on an intersection of two corresponding line of position curves.

Abstract: Systems and methods are presented for passive location of transmitters in which two or more receivers time stamp received signals from target transmitters and the time stamped data for each target signal of interest is isolated to identify a peak power time of arrival for the signal at each transmitter from which differential scan observation values are derived, and for each signal of interest a line of position curve is computed based on the differential scan observation value and corresponding receiver locations, and for each signal of interest an estimated target transmitter location is determined based on an intersection of two corresponding line of position curves.