Abstract: An improved system and technique for processing a communications session in a data communications system suitably includes the steps of receiving the communications session at a line interface card, embedding the communications session into an asynchronous transfer mode (ATM) virtual circuit at the line interface card, transporting the virtual circuit from the line interface card to a processor card via a backplane. The processor card suitably extracts the communications session from the virtual circuit, and processes the communications session as appropriate.

Abstract: An improved system and technique for processing a communications session in a data communications system suitably includes the steps of receiving the communications session at a line interface card, embedding the communications session into an asynchronous transfer mode (ATM) virtual circuit at the line interface card, transporting the virtual circuit from the line interface card to a processor card via a backplane. The processor card suitably extracts the communications session from the virtual circuit, and processes the communications session as appropriate.

Abstract: In a method for switching between multiple system hosts (154,164,174,184) on a CompactPCI bus (110,120), a hot swap controller (166,186) provides to a special arbiter (820) a high priority request signal and the special arbiter (820) provides to the hot swap controller a grant signal only when the CompactPCI bus is idle. The hot swap controller (166,186) provides to the special arbiter (820) a float signal causing the special arbiter (820) to disable the system host signals, which include one or more grant signals for granting bus access to devices on the CompactPCI bus (110,120), one or more reset signals for resetting the devices, one or more interrupts and one or more clock signals provided to devices. The hot swap controller (166,186) transfers control of the CompactPCI bus (110,120) to a standby system host 154,164,174,184).

Abstract: In a method for swapping a system host board (150,160,170,180), when a failure is detected on a first system processor board (150), control of a first CompactPCI bus (110) is transferred from a first system processor board system host (154) to a first bridge board system host(164). In an active/standby configuration, control of a second CompactPCI bus (120) is transferred from a second bridge board system host (184) to a second system processor board system host (174), and control of the devices on the first CompactPCI bus (110) and second CompactPCI bus (120) is transferred from the first system processor (152) to the second system processor (172) without resetting any devices on the system.