Patents by Inventor Charles Clayton

Charles Clayton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180061408
    Abstract: An automated assistant automatically recognizes speech, decode paraphrases in the recognized speech, performs an action or task based on the decoder output, and provides a response to the user. The response may be text or audio, and may be translated to include paraphrasing. The automatically recognized speech may be processed to determine partitions in the speech, which may be in turn processed to identify paraphrases in the partitions. A decoder may process an input utterance text to identify paraphrases content to include in a segment or sentence. The decoder may paraphrase the input utterance to make the utterance, updated with one or more paraphrases, more easily parsed by a parser. A translator may process a generated response to make the response sound more natural. The translator may replace content of the generated response with paraphrase content based on the state of the conversation with the user, including salience data.
    Type: Application
    Filed: August 4, 2017
    Publication date: March 1, 2018
    Applicant: Semantic Machines, Inc.
    Inventors: Jacob Daniel Andreas, David Ernesto Heekin Burkett, Pengyu Chen, Jordan Rian Cohen, Gregory Christopher Durrett, Laurence Steven Gillick, David Leo Wright Hall, Daniel Klein, Adam David Pauls, Daniel Lawrence Roth, Jesse Daniele Eskes Rusak, Yan Virin, Charles Clayton Wooters
  • Publication number: 20170357456
    Abstract: Representative embodiments disclose how to remove spilled data from an unauthorized system and/or service in a cloud service. Some embodiments allow a user to remove spilled data in a secure fashion without involving an administrator. Spilled data resides in a data structure backed by allocated storage locations. The system presents a user interface allowing a user to enter information that allows identification of the allocated storage locations. The spilled data is removed from the data structure leaving whitespace in the allocated storage locations where remnants of the spilled data can reside. The system creates a copy of the data structure, removing the whitespace. The system connects the copy of the data structure in place of the original data structure. The original allocated storage locations are then overwritten in a secure manner to remove any remnants of the spilled data.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 14, 2017
    Inventors: Geoffrey Naismith DeFilippi, Joel D. Tipke, Michael Ernest Bailey, Charles Clayton Gardner, Grant D. Goodall
  • Publication number: 20170345894
    Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: James Fred Salzman, Charles Clayton Hadsell
  • Patent number: 9783868
    Abstract: A dross processing system crucible comprising a substantially vertical inner wall having an upper end, a lower end, an outer surface, and an inner surface, a bottom having an upper surface and a lower surface, the upper surface affixed to the lower end of the inner wall. A blockable port is disposed in the bottom, and a thermal insulating material covers the outer surface of the vertical inner wall and the lower surface of the bottom. An outer vessel is affixed to the upper end of the substantially vertical inner wall, and the thermal insulating material is disposed between the outer surface of the inner wall and the outer vessel.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 10, 2017
    Inventor: Charles Clayton Wycuff
  • Patent number: 9741791
    Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 22, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Fred Salzman, Charles Clayton Hadsell
  • Publication number: 20170140125
    Abstract: Systems and methods for monitoring accurate, real-time medicament device events, performing analytics on that data, and providing notifications are described. In various embodiments, an application server receives controller medication events, analyzes the events, associated event times, and controller medication dosage plans to characterize event times and send notifications for future doses. The controller medication dosage plan may specify a dose time for a planned dose, a narrow time window comprising the dose time, and an expanded time window comprising the narrow time window and longer in duration than the narrow time window, and the events may be characterized based on their time relative to the dose time, the time windows, and other events.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 18, 2017
    Inventors: Christopher Hogg, Gregory F. Tracy, John David Van Sickle, Dmitry Stupakov, Ki Hong Han, Mike Lohmeier, John Kalmi, Leah Morrell, Charles Clayton Donaldson
  • Publication number: 20160190237
    Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: James Fred Salzman, Charles Clayton Hadsell
  • Patent number: 9281245
    Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: March 8, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Fred Salzman, Charles Clayton Hadsell
  • Publication number: 20150159238
    Abstract: A dross processing system crucible comprising a substantially vertical inner wall having an upper end, a lower end, an outer surface, and an inner surface, a bottom having an upper surface and a lower surface, the upper surface affixed to the lower end of the inner wall. A blockable port is disposed in the bottom, and a thermal insulating material covers the outer surface of the vertical inner wall and the lower surface of the bottom. An outer vessel is affixed to the upper end of the substantially vertical inner wall, and the thermal insulating material is disposed between the outer surface of the inner wall and the outer vessel.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Inventor: Charles Clayton WYCUFF
  • Publication number: 20140245864
    Abstract: A dross processing system crucible comprising a substantially vertical inner wall having an upper end, a lower end, an outer surface, and an inner surface, a bottom having an upper surface and a lower surface, the upper surface affixed to the lower end of the inner wall. A blockable port is disposed in the bottom, and a thermal insulating material covers the outer surface of the vertical inner wall and the lower surface of the bottom. An outer vessel is affixed to the upper end of the substantially vertical inner wall, and the thermal insulating material is disposed between the outer surface of the inner wall and the outer vessel.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Inventor: Charles Clayton WYCUFF
  • Publication number: 20140183707
    Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.
    Type: Application
    Filed: December 10, 2013
    Publication date: July 3, 2014
    Inventors: James Fred SALZMAN, Charles Clayton HADSELL
  • Publication number: 20130126508
    Abstract: A method of increasing the operating life of a semiconductor device that is to be used in a harsh ionizing radiation environment including determining heating criteria for annealing the device; installing the device in an electronic apparatus; and heating the installed device with a local heating source in accordance with the heating criteria.
    Type: Application
    Filed: December 1, 2011
    Publication date: May 23, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: James Fred Salzman, Charles Clayton Hadsell
  • Patent number: 5874159
    Abstract: This invention relates to making nonwoven fabrics which are durable for machine washing and durable for other wet and hard use or abusive applications. The inventive fabrics comprise two layers of fabric sheet bonded together at closely spaced locations where the bonding includes fibers from both fabrics thoroughly involved with the binder. The inventive fabrics retain the qualities of a spunlaced nonwoven fabric which include low cost, comfort, drapability, softness, absorbency, breathability and others while having the durability comparable to traditional knitted or woven fabrics.
    Type: Grant
    Filed: May 3, 1996
    Date of Patent: February 23, 1999
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Charles Clayton Cruise, Robert Howe Peterson, James Thomas Summers
  • Patent number: 4413674
    Abstract: A transformer cooling structure characterized by a plurality of coolant fluid cooling panels extending outwardly from the transformer tank wall, and the panels being comprised of a pair of sheet-like sides formed to a corrugated configuration through which the fluid flows in heat exchange with ambient air.
    Type: Grant
    Filed: March 4, 1983
    Date of Patent: November 8, 1983
    Assignee: Westinghouse Electric Corp.
    Inventors: Randall N. Avery, Charles A. Clayton, Levon R. Floyd, Douglas B. Mackintosh, Willie A. Powell, Michael W. Atkins
  • Patent number: 4085049
    Abstract: A skimming device for removing oil and similar products from the surface of water. The device is self-adjusting in that its skimming rate and the depth of skim are controlled by the rate that the skimmed fluid is removed from the device.
    Type: Grant
    Filed: May 4, 1976
    Date of Patent: April 18, 1978
    Inventors: Norman John Reid Hartwick, Donald Charles Clayton Lathe