Abstract: The present invention is achieved by layering a dielectric slab between a ground plane and a two dimensional quasi quantum well heterostructure and by switching between an unbiased state and a negative potential which is established between the quantum well heterostructure and the ground plane. In the unbiased state, the device supports wave propagation in the dielectric with a phase velocity similar to that of a wave propagating in a parallel plate waveguide. Upon application of the bias voltage, that is establishing a negative potential difference between contacts based on either side of the quantum well heterostructure, the conductivity of the quantum well decreases. Therefore, as the carrier wave propagates the wave interacts with a boundary similar to that of a dielectric-air interface. This new boundary condition, in turn, produces a faster phase velocity. Hence, toggling the bias modulates the quantum well conductivity which changes the phase velocity of the carrier wave.

Abstract: A hybrid antenna in which the flared end of a parallel plate of a transmion line is coupled to a frequency independent antenna so as to take the place of the higher frequency radiating portion of the antenna.

Abstract: The present invention is a superconducting opto-electronic phase shifter which is achieved by illuminating a superconducting microstrip line, which is fabricated on a dielectric substrate, with an optical beam of a predetermined intensity and shape. Because the superconducting microstrip will exhibit a local surface resistance when and where illuminated, the microstrip line will be artificially narrowed thereby producing a phase shift. This occurs because as the width of a superconducting microstrip line narrows the velocity of the carder signal increases. Therefore, if the illumination of the superconducting microstrip line causes a local surface resistance, then the surface impedance of the microstrip line is increased causing the effective width of the microstrip line to decrease. Hence, the artificial decrease in the width of the microstrip will cause the phase of the carrier signal to shift.

Abstract: The present disclosure is directed to a technique for assigning each of a plurality of test points (34) on a first surface of a translator board (24) to an appropriate one of a set of grid points (36) on an opposed surface of the board. Such an assignment is accomplished by first mapping the grid points (36) and a successive one of the test points (34) into an array (49a) of uniformly spaced cells (49b). An initial group of cells (49b), surrounding the mapped test point (34), is then searched to locate the four grid points (36) closest to the test point. Among the four closest grid points (36), the one which satisfies a particular constraint is designated. A check is then made to determine whether the designated grid point (36) is appropriate for the test point (34). If so, the grid point (36) is assigned to the test point (34) and the grid point is removed from the array before mapping the next test point.

Abstract: A high frequency test fixture (40) comprises an array of Euler column probes (57,58,59) positioned between a circuit board or substrate under test (41) and a routing board or substrate (42) connected to an electronic tester. The Euler column probes are held in a compliant conducting medium (53) interposed between the circuit under test and the routing board. Electrical insulation (67,68) is placed around each alternate probe of the array of probes to isolate it from the compliant conducting medium. Such an alternate probe is to be used as a test signal driving probe. The probes adjacent to and surrounding a test signal driving probe are in electrical contact with the compliant medium and are to be used as ground probes. A high frequency test signal applied to the circuit under test via one of the alternate probes follows a return current path along the outside perimeter of the compliant medium thereby substantially reducing noise and effective lead inductance of the test fixture (FIG. 2).

Abstract: A driver circuit for alternately sourcing current to, and sinking current from a load (12) comprises a pair of field effect transistors (20 and 22), each having its drain-to-source portion coupled between the load and a separate one of a pair of voltage sources (V.sub.H and V.sub.L) which serve to source and sink current, respectively. Each of a second pair of field effect transistors (24 and 26) has its drain-to-source portion coupled between the gate of a separate one of the first pair of field effect transistors and a current source (28). The gate of each of the field effect transistors of the second pair is supplied with a separate one of a pair of electrical signals V.sub.i ' and V.sub.i '* which alternately shift in amplitude. The control signals V.sub.i ' and V.sub.i '* render the field effect transistors of the second pair alternately nonconductive, thereby rendering the first pair of field effect transistors (20 and 22) alternately conductive to sink and source current, respectively.

Abstract: A sheet (10) of anisotropically conductive material may be fabricated by mixing a quantity of electrically conductive, ferromagnetic particles (16), typically spheres, in an uncured polymer (12). The polymer is then cured in a magnetic field which causes the particles to align in chains (14) each parallel to the lines of the field. In accordance with the invention, a spatially varying magnetic field, comprised of first and second substantially uniformly spaced regions (22 and 24) of high and low field strength, respectively, is applied to the polymer (12) during curing. The difference in the strength of the magnetic field in the first and second regions is such as to give rise to a lateral force on the particles which urges them into the first regions of high field strength where the particles align into chains. Since the first regions of high field strength are substantially uniformly spaced, the chains of particles in the polymer will be likewise substantially uniformly spaced.

Abstract: A driver circuit (10) for sourcing current to, and sinking current from, a load (12) comprises a pair of field effect transistors (18,20) each having their gate-to-source portion coupled between the load and one of a pair of voltage sources which serve to sink and source current, respectively. First and second bias networks (48,119) are each coupled to the gate and source of each of the field effect transistors, respectively. First and second junction transistors (42 and 100) are each coupled between a separate one of the first and second bias networks ( 48 and 119), respectively, and a current source (64) to provide a conductive path therebetween. The first junction transistor is rendered conductive to pass current to the first bias network so that a voltage of sufficient magnitude appears between the source and gate of the first field effect transistor to prevent the conduction thereof.

Abstract: The routing of non-crossing conductive paths (24--24) between each of two families of conductive nodes (18--18) and (20--20) on a surface (15) of a substrate (14) can be facilitated using electrostatic analog. To route the conductive paths (24--24), a two dimensional electrostatic force field is mathematically simulated on the surface (15) by attributing an equal charge to each of the nodes (18--18) of one family opposite that attributed to the nodes (20--20) of the other family, such that the total sum of the charges is zero. Lines of electric flux within the simulated force field are located and a set of flux lines, which link one of the nodes in one family to a separate node in the other family, is then selected. The flux lines in the set are non-crossing because of the properties of the simulated electric field and further a 1:1 matching between nodes (18--18 and 20--20) by the selected set of flux lines is guaranteed.

Abstract: A high frequency test fixture (90) comprises a plurality of double-sided spring-loaded backdriving pins (99) positioned between a circuit board under test (41) and a stripline board (91) connected to an electronic tester. The double-sided backdriving pins (99) are located within through holes (98) of a ground plane (94) interposed between the circuit board (41) and the stripline (91). The top and bottom surfaces (96, 97) of the ground plane (94), respectively facing the circuit board (41) and the stripline board (91), are coated with an insulating material (68, 69). A plurality of pairs of spring-loaded ground pins (109, 111) are located in the ground plane (94) adjacent to the backdriving pins (99).