Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. Based on information in the packet, the lookup front-end can optimize start times for sending key requests as a continuous stream with minimal delay. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.

Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. Based on information in the packet, the lookup front-end can optimize start times for sending key requests as a continuous stream with minimal delay. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.

Abstract: For use in a computer system having a bus coupled to first and second devices and network interface circuitry, a system for, and method of, allowing one of the first and second devices to communicate with a computer network via the network interface circuitry and a computer system incorporating the system or the method. In one embodiment, the system includes: (1) transport stack circuitry, coupled between the bus and the network interface circuitry, that provides socket-layer access to the network interface circuitry via the bus and (2) channel control circuitry, associated with the transport stack circuitry, that establishes unique channels for allowing peer-to-peer, socket-layer access between the first and second devices and the transport interface circuitry within the computer system.

Abstract: A data communications network in which multiple host processors are linked in a network by respective network interface systems. The data communications network transmits packet data containing video information. The network interface system includes circuitry which enables it to direct video data values received from the network directly to a frame buffer or preprocessor to the frame buffer in the host processor. The circuitry determines the destination for each packet, frame buffer or main memory, based on an identifier contained in the packet header. Circuitry routes video data directly to a frame buffer memory area or preprocessor to the frame buffer memory area in the host. The network interface system also includes circuitry which enables it to receive video data directly from a camera memory area in a host processor for transmission on the network. Circuitry generates data packets directly from video data held in a camera memory area where the video data was generated by a camera in the host.

Abstract: A clock generator uses coarse and fine phase locking to lock an internal clock signal to an intermittently received data signal. The clock generator uses separate coarse and fine phase locked loops (PLL's). The respective voltage controlled oscillators (VCO's) of the PLL's are made from matched components and the coarse control signal is applied to both VCO's. The fine PLL locks the output signal provided by the second PLL in phase to the received data signal. The oscillatory signal provided by the second PLL is the output clock signal of the system. The fine phase control signal is combined with the coarse frequency control signal to generate the control signal for the second VCO. The fine phase control signal is generated by comparing transitions in a non-return to zero (NRZ) encoded data signal to corresponding transitions in the output clock signal.

Abstract: A data communications network in which multiple host processors are linked in a ring network by respective network interface processors or nodes includes circuitry in each of the nodes which aids in the implementation of a distributed resource locking scheme and a reliable multicasting system. The circuitry includes a packet generator which automatically generates specialized packets that are used to procure resource locks and to implement the multicast system. In addition, the node includes circuitry which may be used to modify the contents of a received packet and circuitry which automatically retransmits the packet onto the network. The node is controlled by a set of state machines which implement the resource locking and multicasting protocols. In addition, the nodes include circuitry which detects congestion in the node and in the network and acts automatically to relieve the congestion.