Patents by Inventor Charles D Wait

Charles D Wait has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Unified translation miss queue for multiple address translation modes
    Patent number: 11734188
    Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles D. Wait, David Campbell, Jake Truelove, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
  • Sleeping and waking-up address translation that conflicts with translation level of active page table walks
    Patent number: 11636043
    Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 25, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles D. Wait, Jake Truelove, David Campbell, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
  • SLEEP / WAKE-UP PERFORMANCE ENHANCING FOR SIMULTANEOUS ADDRESS TRANSLATION TABLE WALKS
    Publication number: 20230062909
    Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Charles D. Wait, Jake Truelove, David Campbell, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
  • Power optimized prefetching in set-associative translation lookaside buffer structure
    Patent number: 11556475
    Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait, Jody Joyner
  • POWER OPTIMIZED PREFETCHING IN SET-ASSOCIATIVE TRANSLATION LOOKASIDE BUFFER STRUCTURE
    Publication number: 20220309000
    Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait, Jody Joyner
  • UNIFIED TRANSLATION MISS QUEUE FOR MULTIPLE ADDRESS TRANSLATION MODES
    Publication number: 20220292028
    Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Inventors: Charles D. Wait, David Campbell, Jake Truelove, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
  • Determining page size via page table cache
    Patent number: 11422947
    Abstract: A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: August 23, 2022
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Jake Truelove, Charles D. Wait, Jon K. Kriegel
  • DETERMINING PAGE SIZE VIA PAGE TABLE CACHE
    Publication number: 20220050792
    Abstract: A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.
    Type: Application
    Filed: August 12, 2020
    Publication date: February 17, 2022
    Inventors: David Campbell, Jake Truelove, Charles D. Wait, Jon K. Kriegel
  • Promotion of ERAT cache entries
    Patent number: 11221957
    Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 11, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody Joyner, Jon K. Kriegel, Charles D. Wait
  • Reducing translation latency within a memory management unit using external caching structures
    Patent number: 10671537
    Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Jody B. Joyner, Ronald N. Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait, Frederick J. Ziegler
  • Reducing translation latency within a memory management unit using external caching structures
    Patent number: 10649902
    Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Jody B. Joyner, Ronald N. Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait, Frederick J. Ziegler
  • PROMOTION OF ERAT CACHE ENTRIES
    Publication number: 20200073817
    Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody Joyner, Jon K. Kriegel, Charles D. Wait
  • Ensuring forward progress for nested translations in a memory management unit
    Patent number: 10380031
    Abstract: Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Jody B. Joyner, Jon K. Kriegel, Bradley Nelson, Charles D. Wait
  • Ensuring forward progress for nested translations in a memory management unit
    Patent number: 10318435
    Abstract: Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Jody B. Joyner, Jon K. Kriegel, Bradley Nelson, Charles D. Wait
  • Instruction predication using instruction address pattern matching
    Patent number: 10261793
    Abstract: A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Branch prediction with power usage prediction and control
    Patent number: 10067556
    Abstract: A method maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Branch prediction with power usage prediction and control
    Patent number: 10042417
    Abstract: A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL
    Publication number: 20160313788
    Abstract: A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Branch prediction with power usage prediction and control
    Patent number: 9395804
    Abstract: A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait