Patents by Inventor Charles D Wait
Charles D Wait has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11734188Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.Type: GrantFiled: March 11, 2021Date of Patent: August 22, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles D. Wait, David Campbell, Jake Truelove, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Patent number: 11636043Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.Type: GrantFiled: August 30, 2021Date of Patent: April 25, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles D. Wait, Jake Truelove, David Campbell, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Publication number: 20230062909Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Charles D. Wait, Jake Truelove, David Campbell, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Patent number: 11556475Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.Type: GrantFiled: March 29, 2021Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait, Jody Joyner
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Publication number: 20220309000Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.Type: ApplicationFiled: March 29, 2021Publication date: September 29, 2022Inventors: David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait, Jody Joyner
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Publication number: 20220292028Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Charles D. Wait, David Campbell, Jake Truelove, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Patent number: 11422947Abstract: A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.Type: GrantFiled: August 12, 2020Date of Patent: August 23, 2022Assignee: International Business Machines CorporationInventors: David Campbell, Jake Truelove, Charles D. Wait, Jon K. Kriegel
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Publication number: 20220050792Abstract: A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.Type: ApplicationFiled: August 12, 2020Publication date: February 17, 2022Inventors: David Campbell, Jake Truelove, Charles D. Wait, Jon K. Kriegel
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Patent number: 11221957Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).Type: GrantFiled: August 31, 2018Date of Patent: January 11, 2022Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody Joyner, Jon K. Kriegel, Charles D. Wait
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Patent number: 10671537Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.Type: GrantFiled: August 22, 2017Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Jody B. Joyner, Ronald N. Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait, Frederick J. Ziegler
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Patent number: 10649902Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.Type: GrantFiled: November 21, 2017Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Jody B. Joyner, Ronald N. Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait, Frederick J. Ziegler
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Publication number: 20200073817Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).Type: ApplicationFiled: August 31, 2018Publication date: March 5, 2020Inventors: Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody Joyner, Jon K. Kriegel, Charles D. Wait
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Patent number: 10380031Abstract: Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.Type: GrantFiled: November 27, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Jody B. Joyner, Jon K. Kriegel, Bradley Nelson, Charles D. Wait
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Patent number: 10318435Abstract: Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.Type: GrantFiled: August 22, 2017Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Jody B. Joyner, Jon K. Kriegel, Bradley Nelson, Charles D. Wait
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Patent number: 10261793Abstract: A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.Type: GrantFiled: December 16, 2011Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
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Publication number: 20190065398Abstract: Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: GUY L. GUTHRIE, JODY B. JOYNER, JON K. KRIEGEL, BRADLEY NELSON, CHARLES D. WAIT
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Publication number: 20190065399Abstract: Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.Type: ApplicationFiled: November 27, 2017Publication date: February 28, 2019Inventors: GUY L. GUTHRIE, JODY B. JOYNER, JON K. KRIEGEL, BRADLEY NELSON, CHARLES D. WAIT
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Publication number: 20190065380Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.Type: ApplicationFiled: November 21, 2017Publication date: February 28, 2019Inventors: GUY L. GUTHRIE, JODY B. JOYNER, RONALD N. KALLA, MICHAEL S. SIEGEL, JEFFREY A. STUECHELI, CHARLES D. WAIT, FREDERICK J. ZIEGLER
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Publication number: 20190065379Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: GUY L. GUTHRIE, JODY B. JOYNER, RONALD N. KALLA, MICHAEL S. SIEGEL, JEFFREY A. STUECHELI, CHARLES D. WAIT, FREDERICK J. ZIEGLER
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Publication number: 20180300255Abstract: Maintaining agent inclusivity within a distributed memory management unit (MMU) including receiving, from an agent, a translation checkout request comprising an effective address (EA) and an effective address to real address table (ERAT) index; translating the EA to a real address (RA) using an entry in a translation lookaside buffer (TLB) within the MMU, wherein the TLB within the MMU comprises an RA for each EA in the ERAT within the agent; flagging the entry in the TLB as in use by the agent, wherein the entry in the TLB comprises a TLB index; storing the EA index and the TLB index in an in-use scoreboard (IUSB), wherein the IUSB maps TLB indexes identifying entries in the TLB within the MMU to ERAT indexes identifying entries in the ERAT within the agent; and sending, to the agent, a translation checkout response comprising the RA.Type: ApplicationFiled: April 13, 2017Publication date: October 18, 2018Inventors: BARTHOLOMEW BLANER, JODY B. JOYNER, RONALD N. KALLA, JON K. KRIEGEL, CHARLES D. WAIT