Patents by Inventor Charles David Wait
Charles David Wait has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8291201Abstract: A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle so that both such pipeline stages effectively perform steps for the same instruction during each clock cycle. Then, with the selected pipeline stages merged, the power consumption of the execution pipeline can be reduced (e.g., by reducing the clock frequency and/or operating voltage of the execution pipeline), often with minimal adverse impact on performance.Type: GrantFiled: May 22, 2008Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Patent number: 8255674Abstract: A logic arrangement and method to support implied storage operation decode uses redundant target address detection, whereby target addresses of previous instructions are compared with the target address of the current instruction, and if equal, and the target addresses of previous instructions are not used as sources, the current instruction is decoded as a store instruction. This allows a redundant operation in an instruction set architecture to be redefined as a store instruction, freeing up opcodes normally used for store instructions to be used for other instructions.Type: GrantFiled: January 28, 2009Date of Patent: August 28, 2012Assignee: International Business Machines CorporationInventors: Mark Joseph Hickey, Adam James Muff, Matthew Ray Tubbs, Charles David Wait
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Patent number: 8140830Abstract: A circuit arrangement and method utilize a plurality of execution units having different power and performance characteristics and capabilities within a multithreaded processor core, and selectively route instructions having different performance requirements to different execution units based upon those performance requirements. As such, instructions that have high performance requirements, such as instructions associated with primary tasks or time sensitive tasks, can be routed to a higher performance execution unit to maximize performance when executing those instructions, while instructions that have low performance requirements, such as instructions associated with background tasks or non-time sensitive tasks, can be routed to a reduced power execution unit to reduce the power consumption (and associated heat generation) associated with executing those instructions.Type: GrantFiled: May 22, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Patent number: 7814299Abstract: A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.Type: GrantFiled: November 20, 2008Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Mark Joseph Hickey, Adam James Muff, Matthew Ray Tubbs, Charles David Wait
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Publication number: 20100191937Abstract: A logic arrangement and method to support implied storage operation decode uses redundant target address detection, whereby target addresses of previous instructions are compared with the target address of the current instruction, and if equal, and the target addresses of previous instructions are not used as sources, the current instruction is decoded as a store instruction. This allows a redundant operation in an instruction set architecture to be redefined as a store instruction, freeing up opcodes normally used for store instructions to be used for other instructions.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark Joseph Hickey, Adam James Muff, Matthew Ray Tubbs, Charles David Wait
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Patent number: 7752250Abstract: A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or quotient is obtained from a multiply-add hardware pipeline of a floating point processor. Remainders are calculated using the floating point numbers divided, the unit of least precision, and the unit of least precision plus one to determine where the infinitely precise result is with respect to the digital representation of the estimated quotient. Evaluating these remainders and the initial floating point numbers and comparing their signs and magnitudes leads to a selection of one of three choices as the most accurate representation of the infinitely precise result as calculated in the inventive rounding method: the intermediate result minus the unit of least precision; the intermediate divide result; or the intermediate divide result plus the unit of least precision.Type: GrantFiled: January 12, 2006Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventor: Charles David Wait
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Publication number: 20100125719Abstract: A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.Type: ApplicationFiled: November 20, 2008Publication date: May 20, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark Joseph Hickey, Adam James Muff, Matthew Ray Tubbs, Charles David Wait
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Publication number: 20090292907Abstract: A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle so that both such pipeline stages effectively perform steps for the same instruction during each clock cycle. Then, with the selected pipeline stages merged, the power consumption of the execution pipeline can be reduced (e.g., by reducing the clock frequency and/or operating voltage of the execution pipeline), often with minimal adverse impact on performance.Type: ApplicationFiled: May 22, 2008Publication date: November 26, 2009Inventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Publication number: 20090293061Abstract: A circuit arrangement and method utilize a plurality of execution units having different power and performance characteristics and capabilities within a multithreaded processor core, and selectively route instructions having different performance requirements to different execution units based upon those performance requirements. As such, instructions that have high performance requirements, such as instructions associated with primary tasks or time sensitive tasks, can be routed to a higher performance execution unit to maximize performance when executing those instructions, while instructions that have low performance requirements, such as instructions associated with background tasks or non-time sensitive tasks, can be routed to a reduced power execution unit to reduce the power consumption (and associated heat generation) associated with executing those instructions.Type: ApplicationFiled: May 22, 2008Publication date: November 26, 2009Inventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Publication number: 20090182986Abstract: A circuit arrangement and method utilize an issue rate-based predictive thermal management technique in a microprocessor or other integrated circuit that tracks the rate in which instructions are issued to one or more execution units in the processing unit, and selectively delays the issuance of subsequent instructions to the execution unit(s) based upon the tracked issue rate to predictively control the thermal output of the integrated circuit.Type: ApplicationFiled: January 16, 2008Publication date: July 16, 2009Inventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Patent number: 7296108Abstract: An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data transfers transparent to the receiving processor. The alignment mechanism detects an unaligned transfer in the bus command queue and forms multiple commands of aligned data to send to the processor.Type: GrantFiled: May 26, 2005Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Bruce Leroy Beukema, Jamie Randall Kuesel, Robert Allen Shearer, Charles David Wait