Patents by Inventor Charles Dike

Charles Dike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7102402
    Abstract: A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Javed S. Barkatullah, Charles Dike
  • Publication number: 20030221143
    Abstract: A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.
    Type: Application
    Filed: May 23, 2002
    Publication date: November 27, 2003
    Inventors: Nasser A. Kurd, Javed S. Barkatullah, Charles Dike
  • Patent number: 5598113
    Abstract: A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: January 28, 1997
    Assignee: Intel Corporation
    Inventors: Jerry Jex, Charles Dike, Keith Self
  • Patent number: 5539739
    Abstract: An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: July 23, 1996
    Assignee: Intel Corporation
    Inventors: Charles Dike, Robert Gatlin, Jerry Jex, Craig Peterson, Keith Self, Jim Sutton