Abstract: A device implementing an inter-chip time synchronization system may include a first circuit having a first clock and a second circuit having a second clock. The first circuit may be configured to capture a first timestamp from the first clock responsive to receiving a sampling signal from the second circuit. The first circuit may be configured to receive a second timestamp that was captured by the second circuit from a second clock of the second circuit. The second timestamp may have been captured by the second circuit when the sampling signal was transmitted to the first circuit. The first circuit may be configured to generate a conversion parameter for converting from the second clock of the second circuit to the first clock of the first circuit based at least in part on the first and second timestamps, and to store the generated conversion parameter.

Abstract: A device implementing an inter-chip time synchronization system may include a first circuit having a first clock and a second circuit having a second clock. The first circuit may be configured to capture a first timestamp from the first clock responsive to receiving a sampling signal from the second circuit. The first circuit may be configured to receive a second timestamp that was captured by the second circuit from a second clock of the second circuit. The second timestamp may have been captured by the second circuit when the sampling signal was transmitted to the first circuit. The first circuit may be configured to generate a conversion parameter for converting from the second clock of the second circuit to the first clock of the first circuit based at least in part on the first and second timestamps, and to store the generated conversion parameter.

Abstract: A system for synchronizing IQ demodulators includes IQ demodulators, phase-controlling devices, a reference signal, a phase detector, and a control device. The phase-controlling devices are each associated with one of the IQ demodulators for outputting an output signal to its associated IQ demodulator having a phase controlled by the associated phase-controlling device. The phase detector is in communication with the output signals for determining whether the phase of any of the output signals is out-of-phase with a reference phase of the reference signal. The control-device is in communication with the phase-controlling devices programmed, internally or externally, to send a control signal to the associated phase-controlling device for any of the output signals which are out-of-phase with the reference phase of the reference signal so that the associated phase-controlling device synchronizes the phase of the output signal to being in-phase with the reference phase of the reference signal.

Abstract: The battery life of a mobile device operating in a wireless network environment is extended by terminating network communication activities after a specified period of time. Network communication activities may be restored when any one of a specified number of user actions are detected.

Abstract: A system for synchronizing IQ demodulators includes IQ demodulators, phase-controlling devices, a reference signal, a phase detector, and a control device. The phase-controlling devices are each associated with one of the IQ demodulators for outputting an output signal to its associated IQ demodulator having a phase controlled by the associated phase-controlling device. The phase detector is in communication with the output signals for determining whether the phase of any of the output signals is out-of-phase with a reference phase of the reference signal. The control-device is in communication with the phase-controlling devices programmed, internally or externally, to send a control signal to the associated phase-controlling device for any of the output signals which are out-of-phase with the reference phase of the reference signal so that the associated phase-controlling device synchronizes the phase of the output signal to being in-phase with the reference phase of the reference signal.

Abstract: The battery life of a mobile device operating in a wireless network environment is extended by terminating network communication activities after a specified period of time. Network communication activities may be restored when any one of a specified number of user actions are detected.

Abstract: The battery life of a mobile device operating in a wireless network environment is extended by terminating network communication activities after a specified period of time. Network communication activities may be restored when any one of a specified number of user actions are detected.

Abstract: A method and apparatus to reduce the transaction overhead involved with packet I/O on a host bus without sacrificing the latency of packets of important traffic types is described. This involves determining whether a packet is to be aggregated in response to receiving the packet in a receive buffer. If it is determined that the packet should not be aggregated, a host system may be interrupted to indicate availability of the received packet. Subsequently, the packet may be forwarded to an interrupted system via a local bus directly from a receiving buffer without being stored in a local storage. If it is determined that a packet is to be aggregated, it may be stored in a queue in local storage. Subsequently, it may be sent to a host system with a group of other frames using a single bus transaction to eliminate overhead.

Abstract: The battery life of a mobile device operating in a wireless network environment is extended by terminating network communication activities after a specified period of time. Network communication activities may be restored when any one of a specified number of user actions are detected.