Abstract: An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal. The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.

Abstract: An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.

Abstract: A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Abstract: A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Abstract: In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the request, multiple selection units controlled by the mutual exclusion unit, and a two-phase register coupled to at least one of the selection units to transmit data from the selected agent. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the request, multiple selection units controlled by the mutual exclusion unit, and a two-phase register coupled to at least one of the selection units to transmit data from the selected agent. Other embodiments are described and claimed.

Abstract: A data synchronizer is to avoid the pulse width constraint on the data while synchronizing the data between two devices operating at different clock rates. The data synchronizer may comprise one or more storage units such as the flip-flops and a clock gating logic associated with each storage unit. The clock gating logic may generate a control signal which may either allow or stall the clock reaching the storage units. The control signal may be generated by comparing the input and the output to the storage units.

Abstract: An apparatus includes at least one logic storage unit which has a clock input. The apparatus also includes a logic circuit associated with the at least one logic storage unit. The logic circuit is capable of selectively preventing a clock signal from being applied to the clock input of the at least one logic storage unit.

Abstract: An apparatus includes at least one logic storage unit which has a clock input. The apparatus also includes a logic circuit associated with the at least one logic storage unit. The logic circuit is capable of selectively preventing a clock signal from being applied to the clock input of the at least one logic storage unit.

Abstract: Embodiments of the present invention include a two-dimensional C-element array that may be configured to propagate a periodic waveform. The two-dimensional C-element array is advantageous in high-speed clocking applications as in, for example, processors in semiconductor chips.

Abstract: A device and method for improving the synchronization and metastability resolving capabilities of a flip flop. At least one master latch resolves a metastable condition of a received data signal thereby generating a stable data signal which is received and then displayed by a slave latch. Latches with superior metastability time resolution are configured in a master-slave relationship along with a novel clocking scheme whereby the clock signal supplied to the master latch is inverted as compared to that which is supplied to slave latch. As a result, the input data is latched on a falling edge of a clock signal and subsequently displayed on the rising edge of the clock signal providing at one half cycle for the input data to settle before passing out the data thereby allowing metastabilities to resolve during that period.

Abstract: A device and method for improving the synchronization and metastability resolving capabilities of a flip flop. At least one master latch resolves a metastable condition of a received data signal thereby generating a stable data signal which is received and then displayed by a slave latch. Latches with superior metastability time resolution are configured in a master-slave relationship along with a novel clocking scheme whereby the clock signal supplied to the master latch is inverted as compared to that which is supplied to slave latch. As a result, the input data is latched on a falling edge of a clock signal and subsequently displayed on the rising edge of the clock signal providing at one half cycle for the input data to settle before passing out the data thereby allowing metastabilities to resolve during that period.

Abstract: An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net. The apparatus may further comprise back to back inverters where each inverter output is coupled to the other inverter input. The inverters may further comprise a PFET transistor and an NFET transistor, where the PFET transistors have a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors having a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors and the PFET transistors having a back gate bias net. The bias voltage circuit may be further configured to apply a bias voltage when a metastability may occur. The bias voltage circuit may further comprise a NAND gate.

Abstract: A method and apparatus for minimizing a disparity of set and clear bits transmitted across a serial line is disclosed. The method operates by determining a line disparity by examining n-bit datawords that are transmitted. The method also determines a dataword disparity is determined for a dataword yet to be transmitted. The dataword yet to be transmitted is then inverted before transmission if the line disparity and the dataword disparity have the same sign.

Abstract: In a computer system having multiple components, a bidirectional scheme which allows bidirectional data communications between components over a single wire without using termination resistors by placing two drivers from two corresponding processor cores on the same wire, and allowing simultaneous data transfer in two directions. This doubles the effective bandwidth per pin without requiring a modification to the clocking scheme of the system. The driver is impedance matched to the line, and used as the termination for the driver on the opposite end of the wire. This reduces the termination power, since no power is consumed when both drivers are in the same state. The bidirectional flow of data creates a ternary encoding, with a relatively simple decoding possible.

Abstract: An arbiter provides at an output a priority signal that indicates which one of the input signals at an input has gained priority over all other ones. The arbiter comprises a signal processing path between the input and the output for determining the priority signal. The arbiter further comprises a control means coupled to the signal path for detecting (rare) conflicts among priority candidates. In response to the detected conflict, the control means generates control signals to modify the signal path. This conflict-solving part of the arbiter is located outside the signal path. Accordingly, a signal propagation delay in the path is largely independent of the number of input signals.

Abstract: A data transfer system includes a buffer for storing data to be transferred out of the buffer and a register circuit coupled to the buffer for receiving the data from the buffer. The buffer generates a first indication signal when the buffer is almost empty. The buffer generates a second indication signal when the buffer is empty. The register circuit generates a request signal to receive the data from the buffer. The data transfer system further includes a throttling circuit coupled to the buffer and the register circuit for throttling data transmission to the register circuit from the buffer when the buffer generates the first indication signal and for stopping data transmission to the register circuit from the buffer when the buffer generates the second indication signal. The throttling circuit receives the first and second indication signals and the request signal.

Abstract: A multiple-input arbiter first mutually correlates groups of input signals for identifying a particular group, which includes at least one input signal that is a candidate for gaining the overall priority. Thereupon the priority winner is determined in that particular group. Such a hierarchical processing lends itself to an architecture wherein the processing in groups is implemented by cascaded levels of uniform logic blocks. The decomposition in uniform logic blocks considerably simplifies the design of arbiters that process large numbers of input signals.

Abstract: An arbiter based on pairwise mutual exclusion produces an absolute priority signal (G) indicating that one of three or more requests (R.sub.1, R.sub.2, . . . R.sub.N) has gained absolute priority over all the other. At least one mutual-exclusion element (20.sub.1 or 20p) in the arbiter is designed so that its pairwise priority determination car be reversed in response to at least one externally originated test signal (T.sub.1, T.sub.2 or T.sub.M-1, T.sub.M). By doing so after the requests have been asserted in a specified order, a priority conflict can be generated among the requests in order to check the conflict-resolution capability of the arbiter.

Abstract: A D-type flip-flop arrangement includes first and second latches .Circuitry interposed between the latches blocks any metastable condition that may occur in the first latch from propagating into the second latch. Additionally, the arrangement minimizes the likelihood that the first latch will enter a metastable condition and, if it does, resolves the condition extremely rapidly.