Patents by Inventor Charles E. Hunt

Charles E. Hunt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6800212
    Abstract: One embodiment of the present invention provides a system to facilitate using selective etching to form optical components on a circuit device. The system operates by receiving a substrate composed of a first material including a buffer layer composed of a second material. The system forms a sacrificial layer composed of a third material on the buffer layer. Next, the system forms an optical fiber core composed of a fourth material on the sacrificial layer. After the optical fiber core has been formed, the system performs an etching operation using a selective etchant to remove the sacrificial layer. The system also applies a cladding layer to the optical fiber core.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: October 5, 2004
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20040014250
    Abstract: One embodiment of the present invention provides a system that determines the composition of a layer within an integrated device. The system operates by first receiving the integrated device. Next, the system measures properties of the layer using electromagnetic radiation. The properties of the layer measured are used to determine an index of refraction for the layer. The system then solves for the composition of the layer using the index of refraction.
    Type: Application
    Filed: May 13, 2003
    Publication date: January 22, 2004
    Inventors: Jeffrey J. Peterson, Charles E. Hunt, Peter J. Bjeletich
  • Publication number: 20030219937
    Abstract: One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substrate. The system then fabricates multiple layers on this substrate. A layer within these multiple layers includes both strained structures and relaxed structures. These strained structures and relaxed structures are fabricated simultaneously using common fabrication steps.
    Type: Application
    Filed: May 15, 2003
    Publication date: November 27, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20030215968
    Abstract: One embodiment of the present invention provides a system to facilitate using selective etching to form optical components on a circuit device. The system operates by receiving a substrate composed of a first material including a buffer layer composed of a second material. The system forms a sacrificial layer composed of a third material on the buffer layer. Next, the system forms an optical fiber core composed of a fourth material on the sacrificial layer. After the optical fiber core has been formed, the system performs an etching operation using a selective etchant to remove the sacrificial layer. The system also applies a cladding layer to the optical fiber core.
    Type: Application
    Filed: May 15, 2002
    Publication date: November 20, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20030213769
    Abstract: One embodiment of the present invention provides a system that facilitates construction of electromagnetic, optical, chemical, and mechanical systems using chemical endpoint detection. The system operates by receiving a system description that specifies multiple components, including a first component and a second component. The system fabricates the first component and the second component using selected construction materials. The system also creates a first interconnection structure on the first component and a second interconnection structure on the second component. These interconnection structures can be created using a sacrificial layer and chemical endpoint detection. Next, the system brings the first component and the second component together by connecting the first interconnection structure and the second interconnection structure. These interconnection structures align the first component to the second component so that accurate alignment can be achieved.
    Type: Application
    Filed: May 15, 2002
    Publication date: November 20, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6642154
    Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: November 4, 2003
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6559058
    Abstract: One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over the substrate and the second layer. Finally, an etching operation using a selective etchant is used to remove the second layer, thereby leaving the substrate, which forms a first active layer, and leaving the third layer, which forms a second active layer.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: May 6, 2003
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6545299
    Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: April 8, 2003
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20030008519
    Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 9, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6465357
    Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the a second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: October 15, 2002
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20020081861
    Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si—Ge—C), methods for growing Si—Ge—C epitaxial layer(s) on a substrate, etchants especially suitable for Si—Ge—C etch-stops, and novel methods of use for Si—Ge—C compositions are provided. In particular, the invention relates to Si—Ge—C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.
    Type: Application
    Filed: November 13, 2001
    Publication date: June 27, 2002
    Inventors: McDonald Robinson, Richard C. Westhoff, Charles E. Hunt, Li Ling, Ziv Atzmon
  • Patent number: 6064081
    Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: May 16, 2000
    Assignees: Lawrence Semiconductor Research Laboratory, Inc., The Regents of the University of California, The Arizona Board of Regents
    Inventors: McDonald Robinson, Richard C. Westhoff, Charles E. Hunt, Li Ling, Ziv Atzmon
  • Patent number: 6054801
    Abstract: A field emission cathode is provided comprising an emissive member formed of a porous foam carbon material. The emissive member has an emissive surface defining a multiplicity of emissive edges.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: April 25, 2000
    Assignee: Regents, University of California
    Inventors: Charles E. Hunt, Andrei G. Chakhovskoi
  • Patent number: 5961877
    Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: October 5, 1999
    Inventors: McDonald Robinson, Richard C. Westhoff, Charles E. Hunt, Li Ling
  • Patent number: 5906708
    Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: May 25, 1999
    Assignee: Lawrence Semiconductor Research Laboratory, Inc.
    Inventors: McDonald Robinson, Richard C. Westhoff, Charles E. Hunt, Li Ling