Abstract: A network-accessible memory (NAM) element comprises a substrate, a memory mounted to the substrate, network interface circuitry and logic circuitry. The network interface circuitry implements a network physical layer and is mounted to the substrate. The logic circuitry is mounted to the substrate and is coupled to the network interface circuitry and the memory, and is configured to operate as a memory controller to control access to the memory by a host processor which is external to the NAM element through the network interface circuitry. The NAM element can be interconnected with other NAM elements to form a larger NAM storage device.

Abstract: A computer system has a program module verifier and at least first and second program modules. Each program module includes a digital signature and an executable procedure. The first program module furthermore includes a procedure call to the second procedure module, a procedure call to the program module verifier that is logically positioned in the first program module so as to be executed prior to execution of the procedure call to the second program module, and instructions preventing execution of the procedure call to the second program module when the procedure call to the program module verifier results in a verification denial being returned by the program module verifier.

Abstract: A distributed computer system includes a number of microcontrollers adapted into a common architecture neutral network, aggregated by a hierarchy of software engines that provide both connectivity and semantic translation via network servers. The network servers are connected through the network, using architecture neutral command and control programs. A number of first entities are configured to generate a plurality of first messages in a first communication protocol, and a first adapter is configured to convert the first messages of the first protocol to a second communication protocol. A second entity coupled to the first entities is configured to communicate via the first entities via a first adapter, and a third entity, configured to receive the first messages from the first entities, is configured to generate a second message based on the received first messages.

Abstract: A computer system includes a program executer that executes verifiable architecture neutral programs and a class loader that prohibits the loading and execution of non-verifiable programs unless (A) the non-verifiable program resides in a trusted repository of such programs, or (B) the non-verifiable program is indirectly verifiable by way of a digital signature on the non-verifiable program that proves the program was produced by a trusted source. In the preferred embodiment, verifiable architecture neutral programs are Java bytecode programs whose integrity is verified using a Java bytecode program verifier. The non-verifiable programs are generally architecture specific compiled programs generated with the assistance of a compiler. Each architecture specific program typically includes two signatures, including one by the compiling party and one by the compiler. Each digital signature includes a signing party identifier and an encrypted message.

Abstract: A distributed computer system has a program compiling computer and a program executing computer. The program compiling computer is operated by a compiling party and includes a compiler that, when the digital signature of the originating party of an architecture neutral program has been verified, (A) compiles the architecture neutral program code of the architecture neutral program into architecture specific program code in the architecture specific language identified by the compile to information in the architecture neutral program, and (B) appends to the architecture specific program code a digital signature of the compiling party to generate an architecture specific program.

Abstract: A computer system has a program module verifier and at least first and second program modules. Each program module includes a digital signature and an executable procedure. The first program module furthermore includes a procedure call to the second procedure module, a procedure call to the program module verifier that is logically positioned in the first program module so as to be executed prior to execution of the procedure call to the second program module, and instructions preventing execution of the procedure call to the second program module when the procedure call to the program module verifier results in a verification denial being returned by the program module verifier.

Abstract: A computer network having first and second network entities. The first network entity includes a packet object generator that generates a packet object including an executable source method, an executable destination method, and data associated with each of the methods. The first network entity also includes a communications interface to transmit the packet object. The second network entity includes a communications interface to receive the packet object and an incoming packet object handler to handle the received packet object. The incoming packet object handler includes a source and destination verifier to execute the source and destination methods with their associated data so as to verify the source and destination of the received object packet.

Abstract: A computer system has a program module verifier and at least first and second program modules. Each program module includes a digital signature and an executable procedure The first program module furthermore includes a procedure call to the second procedure module, a procedure call to the program module verifier that is logically positioned in the first program module so as to be executed prior to execution of the procedure call to the second program module, and instructions preventing execution of the procedure call to the second program module when the procedure call to the program module verifier results in a verification denial being returned by the program module verifier.

Abstract: A computer system includes a program executer that executes verifiable architecture neutral programs and a class loader that prohibits the loading and execution of non-verifiable programs unless (A) the non-verifiable program resides in a trusted repository of such programs, or (B) the non-verifiable program is indirectly verifiable by way of a digital signature on the non-verifiable program that proves the program was produced by a trusted source. In the preferred embodiment, verifiable architecture neutral programs are Java bytecode programs whose integrity is verified using a Java bytecode program verifier. The non-verifiable programs are generally architecture specific compiled programs generated with the assistance of a compiler. Each architecture specific program typically includes two signatures, including one by the compiling party and one by the compiler. Each digital signature includes a signing party identifier and an encrypted message.

Abstract: A computer network having first and second network entities. The first network entity includes a packet object generator that generates a packet object including an executable source method, an executable destination method, and data associated with each of the methods. The first network entity also includes a communications interface to transmit the packet object. The second network entity includes a communications interface to receive the packet object and an incoming packet object handler to handle the received packet object. The incoming packet object handler includes a source and destination verifier to execute the source and destination methods with their associated data so as to verify the source and destination of the received object packet.

Abstract: A system and method for substantially reducing accidental disclosure of confidential information by interleaving video data frames with video flash frames. These video flash frames preclude an unauthorized person not wearing an appropriate shutter device from intelligibly reading video data frames by influencing the unauthorized person's eye prior to transmission of the video data frame.