Abstract: Control apparatus for a polyphase, brushless dc electric motor includes a programmed microprocessor which responds to signals indicative of rotor position and rotational speed to selectively energize the windings of the motor and effect a desired speed. The apparatus is compact, readily fabricated, and more reliable than hardwired control circuitry.

Abstract: A disk drive control system incorporating an internal microprocessor and internal testing capabilities. The disk drive control system is capable of simulating drive operation without carriage motion so as to test substantially all functional subsystems of the disk drive. The test technique comprises the exercising of subsystems and a diagnosis of operations according to a hierarchy of interdependence of subsystem operation.

Abstract: In a digital information storage system or the like, start up power sequencing for independently operable machines such as disk drives each equipped with a microprocessing unit is provided through a simplified power sequencing circuit. The power sequencing circuit is operatively coupled with an independent preprogrammable micropocessing unit in each machine and to a single control line common to all disk drives. The microprocessing unit is preprogrammed to interact with the power sequencing circuit to provide Enable/Disable signals to the control line and to sense the state of the control line. In particular, the microprocessing unit executes a preprogrammed sequence of steps in interaction with the control line to sequence the start-up of each spindle motor irrespective of the number of disk drives coupled to the control line, thereby preventing electrical power overload.

Abstract: A phase comparator for a digital phase locked loop which provides first and second order error signals for phase and frequency correction of a voltage controlled oscillator in the loop with respect to data being read for self synchronization of the data. A first order error signal is generated in a first phase detector which operates only during a VCO "unsafe" condition, i.e., when a data pulse is beyond a present limit. A finer, second order error signal is generated in a second phase detector which operates only during a VCO "safe" condition, i.e., when a data pulse is within a preset limit.

Abstract: A circuit for discriminating among pulses in a series of recurring pulses based on the interval between adjacent pulses which circuit is particularly useful in extracting timing information from a series of pulses such as are induced in a servo head by movement relative thereto of a prerecorded servo track in a disc pack data storage system. The circuit includes a monostable multivibrator for producing a timing signal having a duration corresponding to the time interval between two successive pulses. The monostable multivibrator output is stored, for example in a data flip flop, so as to produce an output pulse from the flip flop if a succeeding pulse in the series occurs while the monostable multivibrator output is high.

Abstract: A servo system incorporating an attenuator for reducing the error signal an amount proportional to the magnitude of the error signal so as to minimize overshoot without affecting the stability in the system.

Abstract: An improved demodulator principally for receiving dibits from a servo track and generating a position error signal responsive to the servo head position relative to the track as indicated by the dibit signal. The invention improves the functioning of the demodulator for movement of the servo head at both high and low speeds and when noise is encountered in the dibit signal.

Abstract: An improved demodulator principally for receiving dibits from a servo track and generating a position error signal responsive to the servo head position relative to the track as indicated by the dibit signal. The invention improves the capability of the demodulator to operate when noise is encountered in the dibit signal.