Patents by Inventor Charles E. Narad

Charles E. Narad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9294386
    Abstract: Apparatus and computer program product for a programmable packet processing platform for accelerating network infrastructure applications that have been structured so as to separate the stages of classification and action. A pipeline comprising a collection of elements for handling network packets is established under which respective elements are capable of including multiple entries, and respective entries are capable of defining whether the respective entry matches a respective network packet and at least one corresponding action for handling the respective network packet. Defining whether the respective entry matches a respective network packet comprises defining via a predefined set of identifiers to indicate respective network protocol fields of different network protocols. Exemplary actions include dropping packets, forwarding packets, encrypting packets, decrypting packets, and classification of packet flows.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventor: Charles E. Narad
  • Publication number: 20140140342
    Abstract: Methods and apparatus relating to a tightly coupled scalar and Boolean processor are described. In an embodiment, a Boolean unit may include a result vector subunit. The result vector subunit may be controlled by an instruction flow that is managed by a scalar unit. Other embodiments are also disclosed.
    Type: Application
    Filed: September 11, 2013
    Publication date: May 22, 2014
    Inventor: Charles E. Narad
  • Patent number: 8266339
    Abstract: In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: September 11, 2012
    Assignee: Intel Corporation
    Inventor: Charles E. Narad
  • Publication number: 20120110107
    Abstract: In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Inventor: Charles E. Narad
  • Publication number: 20120059956
    Abstract: In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
    Type: Application
    Filed: November 9, 2010
    Publication date: March 8, 2012
    Inventor: Charles E. Narad
  • Patent number: 8117356
    Abstract: In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: February 14, 2012
    Assignee: Intel Corporation
    Inventor: Charles E. Narad
  • Patent number: 7836165
    Abstract: In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventor: Charles E. Narad
  • Patent number: 7831974
    Abstract: A mechanism that associates a mutual exclusion lock with a shared data item and provides ownership of the mutual exclusion lock to multiple execution threads that execute code operating on the shared data item in a sequential order.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: November 9, 2010
    Assignee: Intel Corporation
    Inventors: Larry B. Huston, Charles E. Narad
  • Patent number: 7313140
    Abstract: A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Charles E. Narad, Lawrence B. Huston, Yim Pun, Raymond Ng, Debra Bernstein, Mark B. Rosenbluth
  • Patent number: 7191433
    Abstract: The present application describes a compiler of a network packet classification programming language that generates code for processors such as an application processor and a processing engine. The programming language includes a variety of instructions including an instruction to declare a network protocol and an instruction to specify a rule and at least one action to perform if the rule applies. A processor executing instructions generated by the compiler assigns values based on instructions to declare a network protocol and applies the rule instructions to received packets. The programming language may also include other instructions such as an instruction to search a set of values and identify whether an encapsulated packet header is present in a packet.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: March 13, 2007
    Assignee: Intel Corporation
    Inventors: Charles E. Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M. Rand, Jerry J. Hall
  • Patent number: 7171486
    Abstract: Described herein are techniques to perform reassembly of a Transmission Control Protocol (TCP) data stream from payloads of TCP segments of a bidirectional TCP connection between a first TCP end-point operating at a first network device and a second TCP end-point operating at a second network device.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: January 30, 2007
    Assignee: Intel Corpoartion
    Inventors: Charles E. Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M. Rand, Jerry J. Hall
  • Patent number: 7113985
    Abstract: A mechanism that enables allocation and recovery of buffer resources in both burst access and single access modes of operation is presented.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventors: Charles E. Narad, Larry B. Huston, Alok Mathur, Gregory L. Limes
  • Patent number: 7103821
    Abstract: A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router's network processor.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Charles E. Narad, Lawrence B. Huston, Yim Pun, Kin-Yip Liu
  • Patent number: 7039054
    Abstract: A multi-threaded microprocessor with support for packet header splitting during receive packet processing operations and packet header splicing during transmit packet processing operations, as well as optimized recovery of transmit resources, is presented.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Charles E. Narad, Larry B. Huston, Yim Pun, Raymond Ng
  • Patent number: 6996639
    Abstract: A method includes providing a prefetch cache of entries corresponding to communication rings stored in memory, the communication rings to store information passed from at least one first processing agent to at least one second processing agent. The method also includes detecting that one of the communication rings has an entry, and determining if the communication ring having an entry is to be prefetched. The method further includes prefetching information stored in the communication ring having an the entry by issuing a ring read operation that causes the information to be placed in a corresponding one of the entries in the prefetch cache.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: February 7, 2006
    Assignee: Intel Corporation
    Inventor: Charles E. Narad
  • Patent number: 6859841
    Abstract: The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets, management of buffer flow, encryption services, and management of Network Interface Controllers are accelerated through the use of a multiplicity of specialized modules. A language interface is defined for specifying both stateless and stateful classification of packets and to associate actions with classification results in order to efficiently utilize these specialized modules.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventors: Charles E. Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M. Rand, Jerry J. Hall
  • Publication number: 20040199727
    Abstract: Cache allocation includes a cache memory and a cache management mechanism configured to allow an external agent to request data be placed into the cache memory and to allow a processor to cause data to be pulled into the cache memory.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 7, 2004
    Inventor: Charles E. Narad
  • Publication number: 20040148382
    Abstract: The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets, management of buffer flow, encryption services, and management of Network Interface Controllers are accelerated through the use of a multiplicity of specialized modules. A language interface is defined for specifying both stateless and stateful classification of packets and to associate actions with classification results in order to efficiently utilize these specialized modules.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 29, 2004
    Inventors: Charles E. Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M. Rand, Jerry J. Hall
  • Publication number: 20040143655
    Abstract: The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets, management of buffer flow, encryption services, and management of Network Interface Controllers are accelerated through the use of a multiplicity of specialized modules. A language interface is defined for specifying both stateless and stateful classification of packets and to associate actions with classification results in order to efficiently utilize these specialized modules.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 22, 2004
    Inventors: Charles E. Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M. Rand, Jerry J. Hall
  • Publication number: 20040111540
    Abstract: A method includes providing a prefetch cache of entries corresponding to communication rings stored in memory, the communication rings to store information passed from at least one first processing agent to at least one second processing agent. The method also includes detecting that one of the communication rings has an entry, and determining if the communication ring having an entry is to be prefetched. The method further includes prefetching information stored in the communication ring having an the entry by issuing a ring read operation that causes the information to be placed in a corresponding one of the entries in the prefetch cache.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Inventor: Charles E. Narad