Patents by Inventor Charles E. Seaberg
Charles E. Seaberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9569641Abstract: A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.Type: GrantFiled: March 24, 2015Date of Patent: February 14, 2017Assignee: NXP USA, INC.Inventors: Mohit Arora, Prashant Bhargava, Simon J. Gallimore, Dale J. McQuirk, Charles E. Seaberg
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Patent number: 9467122Abstract: A circuit includes a first transistor having a first current electrode coupled to a first power supply node, a second current electrode coupled to a switching node; a second transistor having a first current electrode coupled to the switching node, a second current electrode coupled to a second power supply node; an inductor having a first terminal coupled to the switching node, a second terminal coupled to an output node; a third transistor having a first current electrode coupled to the output node, a second current electrode coupled to the switching node; a driver circuit configured to transition the switching node from a first voltage to a second voltage by turning on the third transistor to couple the output node to the switching node during a first time period, turning on the first transistor to couple the first power supply node to the switching node during a second time period.Type: GrantFiled: August 29, 2014Date of Patent: October 11, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Charles E. Seaberg, Chang Joon Park
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Publication number: 20160283751Abstract: A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.Type: ApplicationFiled: March 24, 2015Publication date: September 29, 2016Inventors: MOHIT ARORA, Prashant Bhargava, Simon J. Gallimore, Dale J. McQuirk, Charles E. Seaberg
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Patent number: 9294081Abstract: An integrated circuit device includes a driver circuit (100) having a pull-up network with a first pull-up transistor (108) coupled to a second pull-up transistor (110) at a first node (VP), and a pull-down network coupled to the pull-up network including a first pull-down transistor (112) coupled to a second pull-down transistor (114) at a second node (VN). A first bias switch (116) is coupled to the first node. A second bias switch (118) is coupled to the second node. A control circuit (104) is coupled to operate the first and second bias switches. The first bias switch is operated to reduce a voltage at the first node during a pull-down cycle of the driver circuit and the second bias switch is operated to reduce a voltage at the second node during a pull-up cycle of the driver circuit.Type: GrantFiled: March 28, 2014Date of Patent: March 22, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chang Joon Park, Charles E. Seaberg
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Publication number: 20160065047Abstract: A circuit includes a first transistor having a first current electrode coupled to a first power supply node, a second current electrode coupled to a switching node; a second transistor having a first current electrode coupled to the switching node, a second current electrode coupled to a second power supply node; an inductor having a first terminal coupled to the switching node, a second terminal coupled to an output node; a third transistor having a first current electrode coupled to the output node, a second current electrode coupled to the switching node; a driver circuit configured to transition the switching node from a first voltage to a second voltage by turning on the third transistor to couple the output node to the switching node during a first time period, turning on the first transistor to couple the first power supply node to the switching node during a second time period.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: CHARLES E. SEABERG, CHANG JOON PARK
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Publication number: 20150280701Abstract: An integrated circuit device includes a driver circuit (100) having a pull-up network with a first pull-up transistor (108) coupled to a second pull-up transistor (110) at a first node (VP), and a pull-down network coupled to the pull-up network including a first pull-down transistor (112) coupled to a second pull-down transistor (114) at a second node (VN). A first bias switch (116) is coupled to the first node. A second bias switch (118) is coupled to the second node. A control circuit (104) is coupled to operate the first and second bias switches. The first bias switch is operated to reduce a voltage at the first node during a pull-down cycle of the driver circuit and the second bias switch is operated to reduce a voltage at the second node during a pull-up cycle of the driver circuit.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: CHANG JOON PARK, Charles E. Seaberg
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Patent number: 9117507Abstract: Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.Type: GrantFiled: August 9, 2010Date of Patent: August 25, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, Kenneth R. Burch, Charles E. Seaberg
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Patent number: 8537625Abstract: A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.Type: GrantFiled: March 10, 2011Date of Patent: September 17, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, Shayan Zhang, Kenneth R. Burch, Charles E. Seaberg, Andrew C. Russell
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Patent number: 8319548Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.Type: GrantFiled: November 19, 2009Date of Patent: November 27, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, David R. Bearden, Kenneth R. Burch, Charles E. Seaberg, Hector Sanchez, Bradley J. Garni
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Publication number: 20120230126Abstract: A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.Type: ApplicationFiled: March 10, 2011Publication date: September 13, 2012Inventors: Ravindraraj Ramaraju, Shayan Zhang, Kenneth R. Burch, Charles E. Seaberg, Andrew C. Russell
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Publication number: 20120032655Abstract: A circuit including a multistage voltage regulator having a plurality of stages each including a regulated node and a bias transistor. The bias transistors and regulated nodes are configured to control the voltage of the regulated nodes. For at least some of the stages, the regulated nodes are coupled to voltage supply terminals of circuit modules of the stages.Type: ApplicationFiled: August 9, 2010Publication date: February 9, 2012Inventors: Ravindraraj Ramaraju, Kenneth R. Burch, Charles E. Seaberg
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Patent number: 7825720Abstract: A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.Type: GrantFiled: February 18, 2009Date of Patent: November 2, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, David R. Bearden, Kenneth R. Burch, Charles E. Seaberg
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Publication number: 20100207688Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.Type: ApplicationFiled: November 19, 2009Publication date: August 19, 2010Inventors: RAVINDRARAJ RAMARAJU, DAVID R. BEARDEN, KENNETH R. BURCH, CHARLES E. SEABERG, HECTOR SANCHEZ, BRADLEY J. GARNI
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Publication number: 20100207687Abstract: A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.Type: ApplicationFiled: February 18, 2009Publication date: August 19, 2010Inventors: Ravindraraj Ramaraju, David R. Bearden, Kenneth R. Burch, Charles E. Seaberg
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Patent number: 7493179Abstract: Embodiments of the present invention relate generally to digital volume control in digital audio systems. One embodiment relates to a digital audio system having a digital audio processor and a digital volume control coupled to the digital audio processor. The digital volume control includes a feedback loop having an attenuator, and error determination unit, and a filter. The feedback loop determines the attenuation error and shifts the attenuation error beyond a predetermined digital audio range. The output of the digital volume control maintains a substantially constant SNR and THD with respect to the level attenuation over the predetermined digital audio range.Type: GrantFiled: March 25, 2002Date of Patent: February 17, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Octavio A. Gonzalez, Charles E. Seaberg
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Patent number: 7092465Abstract: In order to protect against adjacent channel interference and the effects of weak signal in AM signal processing, pre- and post-AM demodulation filters (36 and 38) may be used where the bandwidth of both is varied in the same manner by a single controlling mechanism (34). In one embodiment, two or more cascaded filters (20, 24 or 22, 26 or 30,32) may be used for the pre- and post-demodulation filters where each of the cascaded filters has a same predetermined order and uses the same set of coefficients. In one embodiment, all cascaded filters are first order IIR filters, which reduces computation complexity. The use of a same set of coefficient for all the cascaded filters results in a same bandwidth for all filters and further reduces computation complexity. In an alternate embodiment, cascaded filters may be used for only one of the pre- and post-demodulator filters.Type: GrantFiled: November 14, 2002Date of Patent: August 15, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Jon Hendrix, Bradley Banks, Charles E. Seaberg
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Patent number: 6760386Abstract: Embodiments of the present invention relate generally to receivers. One embodiment relates to a digital FM receiver having multiple sensors (e.g. antennas). In one embodiment, the digital receiver includes a baseband unit having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating a phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals while another embodiment utlizes a hybrid phase lock loop method. Also, some embodiments of the present invention provide for echo-cancelling after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit to diversity combine and provide echo cancelling for the incoming signals.Type: GrantFiled: July 27, 2001Date of Patent: July 6, 2004Assignee: Motorola, Inc.Inventors: Junsong Li, Jon D. Hendrix, Charles E. Seaberg
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Publication number: 20040096014Abstract: In order to protect against adjacent channel interference and the effects of weak signal in AM signal processing, pre- and post-AM demodulation filters (36 and 38) may be used where the bandwidth of both is varied in the same manner by a single controlling mechanism (34). In one embodiment, two or more cascaded filters (20, 24 or 22, 26 or 30,32) may be used for the pre- and post-demodulation filters where each of the cascaded filters has a same predetermined order and uses the same set of coefficients. In one embodiment, all cascaded filters are first order IIR filters, which reduces computation complexity. The use of a same set of coefficient for all the cascaded filters results in a same bandwidth for all filters and further reduces computation complexity. In an alternate embodiment, cascaded filters may be used for only one of the pre- and post-demodulator filters.Type: ApplicationFiled: November 14, 2002Publication date: May 20, 2004Inventors: Jon Hendrix, Bradley Banks, Charles E. Seaberg
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Patent number: 6658245Abstract: A radio receiver (100) has an IF (intermediate frequency) filter (200) for dynamically adjusting its intermediate frequency. The filter (200) includes a filter bank (301), power/amplitude estimator circuits (308, 310, 312), and weighting circuits (314, 316, 318). The filter bank (301) generates sub-bands, each sub-band having a predetermined frequency range. The power/amplitude estimators (308, 310, 312) provide an estimated power/amplitude in each sub-band. A filter control (320) uses the power/amplitude estimates to determine a percentage of each sub-band signal that is permitted to be coupled a summation circuit (319). The summation circuit (319) sums the weighted sub-band signals to provide a filtered output signal to a demodulator (212).Type: GrantFiled: March 28, 2001Date of Patent: December 2, 2003Assignee: Motorola, Inc.Inventors: Junsong Li, Charles E. Seaberg, Jie Su
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Publication number: 20030182109Abstract: Embodiments of the present invention relate generally to digital volume control in digital audio systems. One embodiment relates to a digital audio system having a digital audio processor and a digital volume control coupled to the digital audio processor. The digital volume control includes a feedback loop having an attenuator, and error determination unit, and a filter. The feedback loop determines the attenuation error and shifts the attenuation error beyond a predetermined digital audio range. The output of the digital volume control maintains a substantially constant SNR and THD with respect to the level attenuation over the predetermined digital audio range.Type: ApplicationFiled: March 25, 2002Publication date: September 25, 2003Inventors: Octavio A. Gonzalez, Charles E. Seaberg