Abstract: A memory system having a moving memory recording media. A sector in each track on the media includes recordings defining a synchronizing field and a start of data field. Selected bit signals of bit signals derived from the recordings are simultaneously combined in a plurality of differing bit signal combinations. The simultaneously validity of all of the bit signals in each of a predetermined number of the differing bit signal combinations, which predetermined number is less than the plurality of bit signal combinations, provides fault tolerant detection of the start of data field.

Abstract: A sector in each track of a moving memory recording media includes recordings defining a synchronizing field and a start of data field. Selected bit signals of bit signals derived from recordings are simultaneously combined in a plurality of differing bit signal combinations. The simultaneous existence or validity of all of the bit signals in each of a predetermined number of differing bit signal combinations, which predetermined number is less than the plurality of bit signal combinations, provides fault tolerant detection of start of data field.

Abstract: A compact, DC-coupled Schmitt trigger circuit is disclosed for providing fast switching in response to differential current signals from an input source such as an amplifier. The circuit includes first and second matched pairs of transistors disposed for performing switching and feedback functions, respectively, and for producing a voltage at an input or base of the first pair equal to the sum (AND function) of the source voltage and the voltage at an emitter of the feedback pair. In response to the applied current signals, the transistors of the second matched pair are always in a conducting state (and requires no extra time to turn on) regardless of the conducting state of either of the transistors of the first matched pair.

Abstract: A gain cell circuit is disclosed having an outer pair of common base transistors and an inner pair of common emitter transistors. External base resistors and emitter resistors are added to the common base transistors for controlling the zero formed by the internal capacitance of the common base transistors, thereby cancelling the dominant pole formed by the common emitter transistors and providing compensation and improvement in gain cell bandwidth.