Patents by Inventor Charles E. Wallace

Charles E. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237223
    Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Charles H. Wallace, Manish Chandhok, Mohit K Haran, Gurpreet Singh, Eungnak Han, Florian Gstrein, Richard E. Schenker, David Shykind, Jinnie Aloysius, Sean Pursel
  • Publication number: 20250046713
    Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Mohit K. HARAN, Reken PATEL, Richard E. SCHENKER, Charles H. WALLACE
  • Patent number: 12218052
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Patent number: 4105331
    Abstract: An apparatus and method to position a moving continuous strip master and a moving continuous strip duplicate for copying film images from the master to the duplicate. A vacuum is applied to a housing, the walls of which are partially formed by surfaces of longitudinally extending adjacent rollers. The master and duplicate are inserted through adjacent roller pairs and both sides exposed to a vacuum within the housing. The master and duplicate are removed from the housing with confronting surfaces in contact through a third adjacent roller pair. As a result of the vacuum created between the confronting strip surfaces and atmospheric pressure on opposite strip surfaces the relative position of the master to the duplicate is maintained until exposure to a light source is complete.
    Type: Grant
    Filed: May 26, 1977
    Date of Patent: August 8, 1978
    Assignee: Extek Microsystems, Inc.
    Inventors: Charles E. Wallace, Donald J. Farmer