Abstract: A dedicated hardware block in the form of a hardware bit coder device for generating IR/RF bit coding protocols. The hardware bit coder device is configurable to any user-defined frame length and single or multiple frame strings. The device can emulate substantially any desired bit coding pattern. The device uses a programmable signal shaping technique that eliminates the need to develop complex bit coding protocols in software. Using the hardware bit coder device of the present invention directly reduces the amount of program memory required by the microcontrollers to accomplish data decoding and also frees up the microcontroller resources for other purposes. The hardware bit coder includes a set of two pattern registers, one corresponding to a high data bit value and the other to a low data bit value. The particular pattern to be shifted out for transmission is defined by the particular data signal. Pattern transmission rate and period are selectable.

Abstract: A difference capture circuit for determining the duration of a digital signal pulse. The difference circuit includes a branch couplable to a standard counter for activating the counter to count as a function of a system clock pulse, and a triggering circuit couplable to a standard capture register for fetching the count from the counter. The difference capture circuit may be incorporated into standard timer unit circuitry and is designed to calculate the difference between either the rise and fall times for an incoming signal, or the rise to rise time of that signal. Adding the difference capture circuit to a timing unit eliminates the need to use RAM, and minimizes processor resources, in obtaining the timing associated with a signal change.

Abstract: A shifting circuit operates on a plurality of input sub-words, that collectively constitute an input data word, to generate a plurality of result sub-words that collectively represent the input data word, shifted. The shifting circuit receives, during each cycle, a separate one of the plurality of input sub-words. A combiner/selector performs a shift on each sub-word provided on the I-bus, taking carry-in bits from a carry-in register. Before a shifting operation is executed, the carry-in register is initialized to zero. (Alternately, the carry-in register may be reset to zero after a shifting operation is executed.) The carry-in register is also connected to receive the sub-words provided by the data source circuit onto the I-bus.