Abstract: A system according to one embodiment includes a collection of computing nodes arranged in a mesh of N×M×Z topology, the nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4; a collection of I/O connections interfaced with one of the sides of the mesh, said side having N×M nodes, each of the I/O connections being tied to a unique one of the nodes in said side; and I/O cards that are tied to the I/O connections.

Abstract: A system according to one embodiment includes a collection of computing nodes arranged in a mesh of N×M×Z topology, the nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4; a collection of I/O connections interfaced with one of the sides of the mesh, said side having N×M nodes, each of the I/O connections being tied to a unique one of the nodes in said side; and I/O cards that are tied to the I/O connections.

Abstract: A method for multiplying two binary numbers includes configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w). The lookup tables can be configured in three layers. The method further includes receiving, by the integrated circuit, an input binary number (d). The method further includes determining, by the integrated circuit, a multiplication result (p) of the known binary number w and the input binary number d by determining each bit (pi) from p using the lookup tables based on specific combinations of bits from the known binary number w and from the input binary number d, wherein a notation jx represents the xth bit of j from the right, with bit j0 being the rightmost bit of j.

Abstract: A computer-implemented method is provided for use with a reconfigurable computational device having a collection of computing nodes arranged in a mesh of N×M×Z topology, the computing nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4. The method includes using the computational device to perform computations characterized by (i) an initial system I/O bandwidth and (ii) an initial system node-to-node latency; reconfiguring the device into a mesh of N?×M?×Z? topology, wherein at least two of N, M, and Z values are different from their corresponding N?, M?, and Z? values, and wherein N×M×Z is equal to N?×M?×Z?; and using the device to perform computations characterized by (i) a modified system I/O bandwidth and (ii) a modified system node-to-node latency.

Abstract: A method for multiplying two binary numbers includes configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w). The lookup tables can be configured in three layers. The method further includes receiving, by the integrated circuit, an input binary number (d). The method further includes determining, by the integrated circuit, a multiplication result (p) of the known binary number w and the input binary number d by determining each bit (pi) from p using the lookup tables based on specific combinations of bits from the known binary number w and from the input binary number d, wherein a notation jx represents the xth bit of j from the right, with bit j0 being the rightmost bit of j.

Abstract: A computer-implemented method is provided for use with a reconfigurable computational device having a collection of computing nodes arranged in a mesh of N× M×Z topology, the computing nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4. The method includes using the computational device to perform computations characterized by (i) an initial system I/O bandwidth and (ii) an initial system node-to-node latency; reconfiguring the device into a mesh of N?×M?×Z? topology, wherein at least two of N, M, and Z values are different from their corresponding N?, M?, and Z? values, and wherein N×M×Z is equal to N?×M?×Z?; and using the device to perform computations characterized by (i) a modified system I/O bandwidth and (ii) a modified system node-to-node latency.

Abstract: A method and system for emulating content-addressable memory (CAM) primitives (e.g., a read operation) is disclosed. According to one embodiment, a method is provided for emulating a read operation on a plurality of CAM elements utilizing a read input including match input data and a CAM element selection index. In the described method, match reference data is distributed among a plurality of random-access memory (RAM) elements by storing match reference data corresponding to each of the plurality of CAM elements within a first RAM element of the plurality. Thereafter, a first record is identified within the first RAM element utilizing a first portion of the match input data and the CAM element selection index. A read operation result is then generated utilizing the first record.

Abstract: A method and system for emulating content-addressable memory (CAM) primitives (e.g., a read operation) is disclosed. According to one embodiment, a method is provided for emulating a read operation on a plurality of CAM elements utilizing a read input including match input data and a CAM element selection index. In the described method, match reference data is distributed among a plurality of random-access memory (RAM) elements by storing match reference data corresponding to each of the plurality of CAM elements within a first RAM element of the plurality. Thereafter, a first record is identified within the first RAM element utilizing a first portion of the match input data and the CAM element selection index. A read operation result is then generated utilizing the first record.

Abstract: An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.

Abstract: An on-the-fly algebraic error correction system and corresponding method for reducing error location search are presented. The method transforms an error locator polynomial into two transformed polynomials whose roots are elements in a smaller subfield, in order to significantly simplify the complexity, and to reduce the latency of the error correcting system hardware implementation. More specifically, if the error locator polynomial is over a finite field of (22n) elements, the transformed polynomial is over a finite subfield of (2n) elements. Thus, the problem of locating the roots of the error locator polynomial is reduced to locating the roots of the transformed polynomials. Assuming the error locator polynomial is of degree m, the present method requires at most (m2/2) evaluations of polynomials over the Galois field GF(22n) and (2n+1) evaluations over the subfield GF(2n) or root finding of two polynomials of at most a degree m over the subfield GF(2n).

Abstract: An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.

Abstract: A method and apparatus for ensuring the integrity of data that can detect errors that remain when the data correction scheme fails to correct at least some of the errors, or has added additional errors. Reed-Solomon check symbols are used for error correction and cyclic redundancy check symbols are used to detect the remaining errors. The roots of the generator polynomials used to generate the Reed-Solomon check symbols and the cyclic redundancy check symbols meet a selected subset of a plurality of conditions. The roots are further selected so that the necessary exponentiation may be performed by a combination of exponentiations by powers of two and multiplications. The Reed-Solomon check symbols are generated based on the data portion of the data block. A deterministically altered data stream is generated based on the data portion of the data block and the cyclic redundancy check symbols are generated based on the deterministically altered data stream.

Abstract: A method and apparatus for ensuring the integrity of data that can detect errors that remain when the data correction scheme fails to correct at least some of the errors, or has added additional errors. Reed-Solomon check symbols are used for error correction and cyclic redundancy check symbols are used to detect the remaining errors. The roots of the generator polynomials used to generate the Reed-Solomon check symbols and the cyclic redundancy check symbols meet a selected subset of a plurality of conditions. The roots are further selected so that the necessary exponentiation may be performed by a combination of exponentiations by powers of two and multiplications. The Reed-Solomon check symbols are generated based on the data portion of the data block. A deterministically altered data stream is generated based on the data portion of the data block and the cyclic redundancy check symbols are generated based on the deterministically altered data stream.

Abstract: A composite encoder/syndrome generating device that both computes check symbols over counterpart data symbol strings to form codewords, and derives syndromes from codewords indicative of their error state. The multistage device provides recursive processing paths at each stage of depth corresponding to the number of symbols concurrently applied to the device. The device is adapted as an encoder when the feed-forward paths between stages are enabled; it is adapted as a syndrome generator upon their disablement. The number of symbols concurrently processed may be varied from clock cycle to clock cycle by conforming the recursion paths per stage to the number of symbols applied as input to the device.

Abstract: A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t≦5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.

Abstract: A system for continuous monitoring and autonomous detection of patterns in the main memory subsystem of a computer system. The invention can be embodied as an extension to existing memory scrubbing hardware to permit stored code pattern analysis and identification during the autonomous transparent memory scrubbing process. A library of stored target signatures is provided to which code signatures are compared during analysis. Code signatures may be derived directly from the memory subsystem data pattern or may be indirectly and more efficiently derived from the error correction code (ECC) string associated with the stored data pattern. This invention is directly applicable to computer virus detection and neutralization systems.

Abstract: A method and means for enhancing the error detection and correction capability obtained when a plurality of data byte strings are encoded in a two-level, block-formatted linear code using code word and block-level redundancy. This is accomplished by vector multiplication of N data byte vectors and a nonsingular invertible integration matrix with nonzero minors with order up to B to secure the necessary interleaving among N data byte vectors to form modified data byte vectors. The selected patterns of interleaving ensure single-pass, two-level linear block error correction coding when the modified data vectors are applied to an ECC encoding arrangement. The method and means are parameterized so as to either extend or reduce the number of bursty codewords or subblocks to which the block-level check bytes can be applied.

Abstract: A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t.ltoreq.5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.

Abstract: The invention relates to an arithmetic unit (AU) in combination with an algebraic block ECC decoder for controlling errors in an electronically recorded digital data message by performing at least one of a plurality of predetermined arithmetic operations on the data message in one or more of a plurality of subfields of a first GF(2.sup.12) or a second GF(2.sup.8) finite field. The arithmetic operations are selected either from a first group of operations associated with a first subfield GF(2.sup.4) as cubically extended to the first finite field GF(2.sup.12) or as quadratically extended to the second finite field GF(2.sup.8), or selected from a second group of operations associated with a second subfield GF(2.sup.6) as quadratically extended to the first finite field GF(2.sup.12).

Abstract: The present invention is a circuit for performing a computation of a plurality of coefficients of an error locator polynomial and a plurality of coefficients of an error evaluator polynomial in a system for correcting errors in a Reed-Solomon encoded datastream, comprising a syndrome generator outputting syndromes of the datastream. The circuit of the present invention is coupled to the syndrome generator and receives the syndromes.