Patents by Inventor Charles Eugene Stroud

Charles Eugene Stroud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7412343
    Abstract: Systems and methods for delay-fault testing field programmable gate arrays (FPGA's), applicable both for off-line manufacturing and system-level testing, as well as for on-line testing within the framework of the roving self-test area (STARs) approach are described. In one described method, two or more paths under test receive a test pattern approximately simultaneously. The two paths are substantially identical and thus should propagate the signal in approximately the same amount of time. An output response analyzer receives the signal from each of the paths and determines the interval between them, and then determines whether a delay fault has occurred based at least in part on the interval. The output response analyzer may include an oscillator and a counter. The oscillator generates an oscillating signal during the interval between when the test signal propagates through the first path and the last path under test.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: August 12, 2008
    Assignee: University of North Carolina at Charlotte
    Inventors: Charles Eugene Stroud, Miron Abramovici
  • Patent number: 6202182
    Abstract: A method of built-in self-testing field programmable gate arrays (FPGAs) including the programmable logic blocks, the programmable routing networks and the programmable input/output cells or boundary ports at the device, board or system level includes testing the programmable logic blocks, reconfiguring a first group of he programmable logic blocks to include a test pattern generator and an output response analyzer, and configuring the programmable routing network into groups of wires under test. This step is followed by generating test patterns propagated along the wires under test and comparing the outputs utilizing the output response analyzer. Based on the result of the comparison a pass/fail test result indication is routed to the associated boundary port. The results from a plurality of output response analyzers can be compared utilizing an iterative comparator in order to reduce the number of boundary ports required during testing.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: March 13, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Miron Abramovici, Charles Eugene Stroud, Sajitha S. Wijesuriya
  • Patent number: 6108806
    Abstract: A method of testing field programmable gate arrays (FPGAs) includes establishing a first group of programmable logic blocks as test pattern generators or output response analyzers and a second group of programmable logic blocks as blocks under test. This is followed by generating test patterns and comparing outputs of two blocks under test with one output response analyzer. Next is the combining of results of a plurality of output response analyzers utilizing an iterative comparator in order to produce a pass/fail indication. The method also includes the step of reconfiguring each block under test so that each block under test is tested in all possible modes of operation. Further, there follows the step of reversing programming of the groups of programmable logic blocks so that each programmable logic block is configured at least once as a block under test.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: August 22, 2000
    Assignees: Lucent Technologies Inc., University of Kentucky Research Foundation
    Inventors: Miron Abramovici, Eric Seng-Kar Lee, Charles Eugene Stroud