Patents by Inventor Charles F. Duffey

Charles F. Duffey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-imprinting memory with high speed erase
    Patent number: 7525836
    Abstract: A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: April 28, 2009
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Robert M. Backus, Charles F. Duffey, Andrew C. Weil, Swati V. Joshi
  • Non-Imprinting Memory with High Speed Erase
    Publication number: 20080192553
    Abstract: A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state.
    Type: Application
    Filed: April 15, 2008
    Publication date: August 14, 2008
    Inventors: Robert M. Backus, Charles F. Duffey, Andrew C. Weil, Swati V. Joshi
  • Non-imprinting memory with high speed erase
    Patent number: 7379325
    Abstract: A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: May 27, 2008
    Assignee: Maxim Intergrated Products, Inc.
    Inventors: Robert M. Backus, Charles F. Duffey, Andrew C. Weil, Swati V. Joshi