Abstract: A vertical cavity surface emitting laser (VCSEL) is disclosed that has a relatively low vertical resistance between the Ohmic contact to the upper distributed Bragg reflector (DBR) and the active layer, and a structure to substantially confine the current flow to the laser cavity so that the VCSEL can produce a more efficient and substantially single-mode output. In particular, the VCSEL includes a substrate, a lower DBR disposed over the substrate, an active layer disposed over the lower DBR, and an upper DBR. The upper DBR includes a groove and an Ohmic contact situated within the groove to lower the vertical resistance between the contact and the active layer. An ion implanted layer is also formed along the side wall of the active layer to substantially confine the current flow to the laser cavity.

Abstract: A vertical cavity surface emitting laser (VCSEL) is disclosed that has a relatively low vertical resistance between the Ohmic contact to the upper distributed Bragg reflector (DBR) and the active layer, and a structure to substantially confine the current flow to the laser cavity so that the VCSEL can produce a more efficient and substantially single-mode output. In particular, the VCSEL includes a substrate, a lower DBR disposed over the substrate, an active layer disposed over the lower DBR, and an upper DBR. The upper DBR includes a groove and an Ohmic contact situated within the groove to lower the vertical resistance between the contact and the active layer. An ion implanted layer is also formed along the side wall of the active layer to substantially confine the current flow to the laser cavity.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises an emitter. The heterojunction bipolar transistor further comprises a first emitter cap comprising a first high-doped layer, a low-doped layer, and a second high-doped layer, where the first high-doped layer is situated on the emitter, the low-doped layer is situated on the first high-doped layer, and the second high-doped layer is situated on the low-doped layer. The first high-doped layer, the low-doped layer, and the second high-doped layer form an emitter ballast resistor. According to this exemplary embodiment, the low-doped layer has a thickness and a dopant concentration level such that the resistance of the low-doped layer is substantially independent of the dopant concentration level, but corresponds to the thickness of the low-doped layer.

Abstract: The present invention performs RF performance measurements on basic transistors of a microwave monolithic integrated circuit while it is being fabricated. The circuitry necessary to assess the performance potential at the frequency and power levels of interest is provided by incorporating matching elements onto RF probes used for in-process tests. This invention measures the RF performance potential of GaAs monolithic microwave integrated circuits at an early stage in the process before expensive process sequence has been completed. The essence of the invention is that the transistors are measured with an RF probe that has RF matching circuitry included as an integral part of the probe. Consequently, the performance potential of circuits on the wafer is assessed at the earliest possible point in the manufacturing process; specifically as soon as Schottky barrier gates have been deposited. This in-process measurement approach may be applied to any microwave monolithic integrated circuit.

Abstract: A device useful both as a switch and power limiter and particularly adapted for use in microwave application. The device is made with conventional FET processing technology, a current conducting layer being formed at a surface of a substrate, the device then being electrically isolated by using any one of a number of conventional processes. Ohmic contacts are deposited to make electrical contact at the conducting layer. A groove is then cut with a focused ion beam across the conducting layer and between the ohmic contacts. The length of the groove controls the threshold voltage for the device and the depth controls the saturation current. Very low values of saturation current can be obtained by controlling the groove dimensions thus significantly reducing the DC power drain when the device is operated just above saturation. A very high differential resistance ratio is obtained by adjusting the threshold voltage of the device.

Abstract: A field effect transistor is provided wherein a semiconductor body has a source region and a plurality of drain regions with a gate region common to the plurality of drain regions. A common gate electrode is formed over the common gate region to control the flow of carriers to each one of the plurality of drain regions. With such arrangement an efficient multi-drain field effect transistor is provided through the use of a common gate electrode formed on the semiconductor body.