Abstract: The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managing a pointer that points to a current top-of-stack register. As data is pushed or popped from the stack, the top-of-stack point is incremented or decremented accordingly.

Abstract: The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that are configured to emulate a top portion of a stack and memory, which contains, the remainder of the stack. Some embodiments utilize a variable buffer that is configured to buffer transfers between the processor registers and the memory. The actual amount of data stored in the variable buffer is configured to be flexible, so that transfers between the variable buffer and processor registers are managed to keep the processor registers filled with active stack data (assuming that stack data exists). However, transfers between the variable buffer and memory may be configured to occur only when the variable buffer exceeds certain fill capacities.

Abstract: A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic. The processor also includes second decoder logic capable of decoding a plurality of encoded instructions comprising a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic. Finally, the processor includes decoder control logic configured to selectively control active operation of the first decoder logic and the second decoder logic. In operation, the decoder control logic operates such that when the first decoder logic is decoding an instruction then the second decoder logic is operated in a lower-power, inactive mode. Likewise, when the second decoder logic is decoding an instruction then the first decoder logic is operated in a lower-power, inactive mode.

Abstract: A system and method for handling a status change in a pipeline microprocessor. The pipeline microprocessor determines, at the decode unit, if an instruction is a status instruction. If the instruction is determined to be a status instruction, the decode unit delays the start of the following instruction a sufficient number of clock cycles to allow the status change to propagate through the system pipeline.

Abstract: The present invention is generally directed to an apparatus and method for accessing registers within a processor. In accordance with one embodiment, an apparatus and method are provided for a processor in which at least two separate indicia (such as register select lines, register bank identifiers, processor mode identifiers, etc.) are utilized to uniquely identify and access a processor register. In accordance with this embodiment, bit lines of the separate indicia are encoded into a single, mapped set of signal lines, and these encoded signal lines are used to access the register.

Abstract: The present invention is generally directed to an apparatus and method for performing a partial flush of a processor pipeline in response to exceptions (e.g., interrupts). In accordance with an aspect of one embodiment a processor is provided with logic that operates to flush only limited stages of a processor pipepline (e.g., stages between the current instruction and the pending interrupt) if the execution of a current instruction will impact the execution of a pending interrupt (e.g., if the current instruction is a branch, if the current instruction would cause the processor to enter a mode that disables the pending interrupt, etc.). In accordance with another aspect of this embodiment, a method is provided for performing a partial flush of processor pipeline if the execution of a current instruction would impact the execution of a pending interrupt.

Abstract: A power saving hierarchical clock gating circuit includes a first level clock gate, a plurality of second level clock gates connected to the first level clock gate, and a plurality of third level clock gates for selectively providing a clock signal to a functional block. Each third level clock gate is connected between a second level clock gate and a register, or other low level device, of the functional block for selectively providing the clock signal to the register. Accordingly, the clock signal is conveyed from the first level clock gate through a second level and a third level clock gate to a register when the corresponding first, second, and third level clock gates are activated by associated decision logic.

Abstract: The present invention is generally directed to an apparatus and method for accessing registers within a processor. In accordance with one embodiment, an apparatus and method are provided for a processor in which at least two separate indicia (such as register select lines, register bank identifiers, processor mode identifiers, etc.) are utilized to uniquely identify and access a processor register. In accordance with this embodiment, bit lines of the separate indicia are encoded into a single, mapped set of signal lines, and these encoded signal lines are used to access the register.

Abstract: The present invention is generally directed to an apparatus and method for performing a partial flush of a processor pipeline in response to exceptions (e.g., interrupts). In accordance with an aspect of one embodiment a processor is provided with logic that operates to flush only limited stages of a processor pipepline (e.g., stages between the current instruction and the pending interrupt) if the execution of a current instruction will impact the execution of a pending interrupt (e.g., if the current instruction is a branch, if the current instruction would cause the processor to enter a mode that disables the pending interrupt, etc.). In accordance with another aspect of this embodiment, a method is provided for performing a partial flush of processor pipeline if the execution of a current instruction would impact the execution of a pending interrupt.

Abstract: A power saving hierarchical clock gating circuit includes a first level clock gate, a plurality of second level clock gates connected to the first level clock gate, and a plurality of third level clock gates for selectively providing a clock signal to a functional block. Each third level clock gate is connected between a second level clock gate and a register, or other low level device, of the functional block for selectively providing the clock signal to the register. Accordingly, the clock signal is conveyed from the first level clock gate through a second level and a third level clock gate to a register when the corresponding first, second, and third level clock gates are activated by associated decision logic.

Abstract: A method and system for terminating unnecessary processing of at least one multi-clock conditional instruction in a processor. The conditional instruction is processed through a processing pipeline including at least a decode stage, an execute stage, and one or more intermediate processing stages therebetween. It is determined whether the conditional instruction is executable in the execute stage based on whether one or more conditions are fulfilled. If the conditional instruction is being processed in both the decode and execute stages, the conditional instruction is terminated in the decode stage if the conditional instruction is not to be executed in the execute stage. The conditional instruction may also be terminated in the intermediate processing stages. Early termination of such a conditional instruction saves processing resources and reduces power consumption of the processor.

Abstract: A method and system is disclosed for predicting whether a conditional instruction is to be executed in a processor. The processor processes instructions through processing stages including at least a decode stage, an execute stage, and one or more intermediate processing stages therebetween. First, a current condition status of the processor is detected, wherein the condition status shows whether one or more conditions for executing the conditional instruction have been satisfied. After detecting whether one or more associated instructions as being processed during the intermediate processing stages have impacted or will impact the conditions to be satisfied, it is determined whether the conditional instruction should be terminated at the decode stage based on the detected current condition status and the detected impact on the conditions due to the processing of the associated instructions.

Abstract: A cache having an internal data memory is provided. The cache includes latching logic coupled to an output of the data memory and configured to latch data output from the data memory. The latch also includes determining logic responsive to a request for data, the determining logic configured to determine whether requested data currently resides in the latching logic. Finally, the latch includes inhibit logic configured to inhibit active operation of the data memory, in response to the determining logic, if it is determined that the requested data currently resides in the latching logic. A related method for reading data from a cache is also provided.

Abstract: A transmission circuit for transmitting data from a host to a remote includes a plurality of memory queues, and a memory controller operable to prefetch a burst of data cells from the host, wherein a first data cell of the burst is transmitted by the memory controller to the remote and the remainder of the data cells of the burst are stored in the plurality of memory queues for later transmission to the remote.

Abstract: A processor having improved decode logic is provided. In accordance with one embodiment, the processor includes a first decoder capable of decoding a first plurality of instructions, a second decoder capable of decoding a second plurality of instructions, and special instruction logic for implementing at least one special instruction, the at least one special instruction being an instruction that the first decoder or second decoder is not designed to directly decode for execution by an execution unit in the processor. In another embodiment, a related method is provided for decoding a processor instruction.

Abstract: A cache is provided that comprises a plurality of cache blocks that are independently selected using a direct-mapped cache access, with each block capable of storing a plurality of cache lines and having a plurality of outputs. The cache further includes comparison logic associated with each of the plurality of cache blocks, each comparison logic having a plurality of inputs for receiving the plurality of outputs of the associated cache block and configured to compare the plurality of outputs of the associated cache block with a value on a portion of an address bus that is input to the cache. Finally, the cache includes output logic for outputting from the cache an output from the comparison logic that is associated with a selected cache block. A related method for caching data is also provided.

Abstract: A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic. The processor also includes second decoder logic capable of decoding a plurality of encoded instructions comprising a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic. Finally, the processor includes decoder control logic configured to selectively control active operation of the first decoder logic and the second decoder logic. In operation, the decoder control logic operates such that when the first decoder logic is decoding an instruction then the second decoder logic is operated in a lower-power, inactive mode. Likewise, when the second decoder logic is decoding an instruction then the first decoder logic is operated in a lower-power, inactive mode.

Abstract: A system and method for handling a status change in a pipeline microprocessor. The pipeline microprocessor determines, at the decode unit, if an instruction is a status instruction. If the instruction is determined to be a status instruction, the decode unit delays the start of the following instruction a sufficient number of clock cycles to allow the status change to propagate through the system pipeline.

Abstract: A method of scheduling transmission of a plurality of cells of a first signal packet associated with a first virtual channel address using a scheduling ring having a plurality of slots and pointer operable to indicate a current slot includes advancing the pointer to a slot associated with the first virtual channel address, initiating transmission of a previously scheduled first cell associated with the first virtual channel address, rescheduling transmission of a previously unscheduled second cell associated with the first virtual channel address for transmission at a later time, and advancing the pointer to the next slot.

Abstract: A data transmission system includes a memory, a remote coupled to the memory by a receive data controller, and a host coupled to the memory by a transmit data controller. The system prioritizes the transmission of data cells from the remote to the host based on demand by dynamically allocating portions of the memory to data cells sharing a common and frequently recurring address at the host, and transmitting to the host incihvidual data cells together in a burst.