Abstract: An XDSL system comprising a hybrid circuit in operative communication with a transmission line and an XDSL modem associated with a subscriber premises. The hybrid circuit comprises a plurality of selectable impedance circuits having different impedance values. A controller selectively engages each of the impedance circuits in-line with the XDSL modem and the transmission line. The controller records the performance of the modem with each circuit engaged, and selects the desired impedance circuit as a function of the performance characteristics associated with each of the impedance circuits. The impedance circuit which provides the best performance characteristic is selected as the impedance circuit for normal modem operation.

Abstract: An XDSL system comprising a hybrid circuit in operative communication with a transmission line and an XDSL modem associated with a subscriber premises. The hybrid circuit comprises a plurality of selectable impedance circuits having different impedance values. A controller selectively engages each of the impedance circuits in-line with the XDSL modem and the transmission line. The controller records the performance of the modem with each circuit engaged, and selects the desired impedance circuit as a function of the performance characteristics associated with each of the impedance circuits. The impedance circuit which provides the best performance characteristic is selected as the impedance circuit for normal modem operation.

Abstract: A two-phase, non-overlapping clock signal is generated in response to a single-phase input clock signal by delaying the input clock signal to produce the first phase output clock signal (.phi..sub.1), producing a delayed signal from the first phase clock signal, and gating the further delayed first phase clock signal with the input clock signal to produce an inverted signal for a second phase clock signal (.phi..sub.2), in order to produce gaps between the trailing edge of one phase of the output clock and the leading edge of the other phase of the output clock signal in order to accommodate dynamic transient conditions that must occur in a following utilization circuit between successive phase clock pulse signals.