Patents by Inventor Charles Frye
Charles Frye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100140742Abstract: A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. A thin film capacitor is formed within the semiconductor device by a first metal plate, dielectric layer over the first metal plate, and second and third electrically isolated metal plates opposite the first metal plate. The terminals are located on the same side of the capacitor.Type: ApplicationFiled: February 15, 2010Publication date: June 10, 2010Applicant: STATS ChipPAC, Ltd.Inventors: Kai Liu, Robert Charles Frye
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Publication number: 20100140738Abstract: A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. In the case of copper, the coil structures have a height greater than 5 micrometers. The first, second, and third coil structures are arranged in rounded or polygonal pattern horizontally across the substrate with a substantially flat vertical profile.Type: ApplicationFiled: February 15, 2010Publication date: June 10, 2010Applicant: STATS ChipPAC, Ltd.Inventors: Kai Liu, Robert Charles Frye
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Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD)
Patent number: 7727879Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.Type: GrantFiled: March 21, 2007Date of Patent: June 1, 2010Assignee: STATS ChipPAC, Ltd.Inventors: Yaojian Lin, Robert Charles Frye -
Publication number: 20100108589Abstract: The present invention relates generally to a fluid filter assemblies. In particular, the present invention is directed to fluid filter assemblies comprising a single-piece tapped plate and retainer.Type: ApplicationFiled: November 3, 2008Publication date: May 6, 2010Applicant: PUROLATOR FILTERS NA LLCInventors: Randy Charles FRYE, Ken MORTON, Sudheer GHADIYARAM
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Patent number: 7688160Abstract: A coil structure for a filter device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil. A portion of the second coil is oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A portion of the third coil is oriented interiorly of the second coil.Type: GrantFiled: April 12, 2007Date of Patent: March 30, 2010Assignee: STATS ChipPAC, Ltd.Inventors: Kai Liu, Robert Charles Frye
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Publication number: 20100045398Abstract: A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.Type: ApplicationFiled: October 27, 2009Publication date: February 25, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Kai Liu, Robert Charles Frye
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Publication number: 20100039185Abstract: A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.Type: ApplicationFiled: October 14, 2009Publication date: February 18, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Kai Liu, Robert Charles Frye
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Publication number: 20100033290Abstract: A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.Type: ApplicationFiled: October 14, 2009Publication date: February 11, 2010Applicant: STATS ChipPAC, LTD.Inventors: Kai Liu, Robert Charles Frye
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Publication number: 20100033289Abstract: A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.Type: ApplicationFiled: October 14, 2009Publication date: February 11, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Kai Liu, Robert Charles Frye
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Patent number: 7629860Abstract: A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between secondhand third portions of the third coil.Type: GrantFiled: June 8, 2007Date of Patent: December 8, 2009Assignee: STATS ChipPAC, Ltd.Inventors: Kai Liu, Robert Charles Frye
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Publication number: 20080303606Abstract: A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between secondhand third portions of the third coil.Type: ApplicationFiled: June 8, 2007Publication date: December 11, 2008Applicant: STATS ChipPAC, Ltd.Inventors: Kai Liu, Robert Charles Frye
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Publication number: 20080252395Abstract: A coil structure for a filter device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil. A portion of the second coil is oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A portion of the third coil is oriented interiorly of the second coil.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: STATS ChipPAC, LTD.Inventors: Kai Liu, Robert Charles Frye
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Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
Publication number: 20080233731Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Applicant: STATS CHIPPAC, LTD.Inventors: Yaojian LIN, Robert Charles FRYE -
Patent number: 7061340Abstract: A differently-tuned voltage controlled oscillator (VCO) and its application in a multi-band VCO tuner are disclosed. In one aspect of the invention, the VCO comprises a plurality of serially connected inductive elements each including inductively coupled inductor elements, a varactor element connected in parallel with the serially connected first inductor elements and means to apply a first and second tuning voltage to elements of the varactor element. In a second aspect, the VCO further comprises a second varactor element connected in parallel with the inductive elements, and means to apply the second tuning voltage elements of the second varactor element.Type: GrantFiled: April 1, 2004Date of Patent: June 13, 2006Assignee: Agere Systems, Inc.Inventors: Vito Boccuzzi, Robert Charles Frye, Sander Lauentius Gierkink
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Publication number: 20040195171Abstract: A fluid filter assembly including a canister having a closed end and an open end; a filter element assembly disposed within the canister and having a first end adjacent the closed end of the canister and a second end adjacent the open end of the canister; and a reversible element guide disposed within the canister between the closed end and the first end of the filter element assembly. The reversible element guide has a first side and a second side, the first side shaped substantially the same as the second side. The reversible element guide is positioned in either a first position, wherein the first side bears against the closed end of the canister or a second position, wherein the second side bears against the closed end of the canister. The reversible element guide may be a wave spring having a ring shape and a plurality of undulations.Type: ApplicationFiled: April 4, 2003Publication date: October 7, 2004Inventor: Randy Charles Frye
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Publication number: 20040196110Abstract: A differently-tuned voltage controlled oscillator (VCO) and its application in a multi-band VCO tuner are disclosed. In one aspect of the invention, the VCO comprises a plurality of serially connected inductive elements each including inductively coupled inductor elements, a varactor element connected in parallel with the serially connected first inductor elements and means to apply a first and second tuning voltage to elements of the varactor element. In a second aspect, the VCO further comprises a second varactor element connected in parallel with the inductive elements, and means to apply the second tuning voltage elements of the second varactor element.Type: ApplicationFiled: April 1, 2004Publication date: October 7, 2004Inventors: Vito Boccuzzi, Robert Charles Frye, Sander Lauentius Gierkink
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Patent number: 6282100Abstract: The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.Type: GrantFiled: July 1, 1999Date of Patent: August 28, 2001Assignee: Agere Systems Guardian Corp.Inventors: Yinon Degani, Thomas Dixon Dudderar, Robert Charles Frye
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Patent number: 6232047Abstract: The specification describes method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip at the edge of the conductive strip.Type: GrantFiled: March 2, 1999Date of Patent: May 15, 2001Assignee: Agere Systems Inc.Inventors: Robert Charles Frye, Yee Leng Low, King Lien Tai
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Patent number: 6175158Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a silicon translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The thermal mismatch between the silicon translator and conventional printed wiring board materials is addressed by using an interposer which is essentially a ball grid array of plated-through holes that transfers the interconnect pattern from the translator to the printed wiring board. The interposer may have a composition with a coefficient of thermal expansion (CTE) that lies between the CTE of silicon and the CTE of the board material. It may also be provided with holes or slots for additional stress relief.Type: GrantFiled: September 8, 1998Date of Patent: January 16, 2001Assignee: Lucent Technologies Inc.Inventors: Yinon Degani, Thomas Dixon Dudderar, Robert Charles Frye, King Lien Tai
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Patent number: 6160715Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The translator also has a large area outboard of the IC chip area to allow fan out from high pin count chips to large pitch interconnection sites for interconnection to the next board level.Type: GrantFiled: September 8, 1998Date of Patent: December 12, 2000Assignee: Lucent Technologies Inc.Inventors: Yinon Degani, Thomas Dixon Dudderar, Robert Charles Frye, King Lien Tai