Abstract: A method and system within a data processing system are disclosed for halting execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal states within the processor. The processor includes a number of state machines and a means for monitoring the states of the number of state machines. According to the present invention, a selected combination of states of a subset of the state machines is specified. An enumerated occurrence of the selected combination of states of the subset of the state machines is then detected. In response to the enumerated occurrence of the selected combination of states, execution of instructions by the processor is halted such that states of the number of state machines within the processor remain substantially unchanged following the enumerated occurrence of the selected combination of states.

Abstract: A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.

Abstract: A data processing system including a processor that executes a plurality of instructions including at least one instruction that requires an external operation to be performed. The processor provides information for this external operation instruction to an external device and continues to execute instructions that do not require the results from this external operation. The external device receives the information from the processor, performs the external operation and provides the results to the processor. A further aspect of this data processing system is an interface that is interconnected between the processor and the external device. The processor provides the external operation information to the interface. The interface in turn provides the information to the external device and concurrently accesses data from the memory that will be required by the external device for performing the external operation.

Abstract: In a data processing system, particularly one implemented by a microprocessor, apparatus is provided for bypassing the main parallel information bus between the processor and main storage unit by a serial information bus for testing purposes. Serial test information is applied through the serial information bus to a storage control unit which interfaces the processor and storage unit. The control includes circuitry for converting the information from the serial bus into the parallel format of the data which is provided from the processor along the main parallel bus. The test information applied has the same commands and address structure as the information output from the central processor. As a result, when the serial test information is converted to parallel format, by the apparatus, it will be indistinguishable from parallel data applied directly from the processor along the parallel bus.

Abstract: A data processing system including several devices connected to an asynchronous communications bus for communications between these devices. The communications bus includes a protocol that requires only a single device to regulate communication between devices at any one time. This regulating device is termed the bus master and the remaining devices are termed slaves. This protocol provides the capability for a slave device to indicate to the bus master that a new bus master is to be designated for a temporary communication. This communication with a different bus master then occurs during the communication of the designated bus master.

Abstract: A plurality of controllers are connected to a common bus in turn connected to a central processor. Each of the controllers respectively serves as an interface between the central processor and at least one storage unit for input/output device. In order for the controllers to distinguish between addresses, the addresses sent from the central processor contain identifier segments indicative of the controller to which the address is being sent. Controllers in turn contain programmable comparison means for comparing the identifier segments in addresses to a stored controller identifier indicative of the controller. Because the comparison means are programmable, controller identifiers have to be set up each time the system is turned on.

Abstract: A plurality of data processor units are connected to a common bus which is connected to first and second interleaved storage units. The system is a synchronous one in which timing means establish a series of information transfer intervals. One or more of the processor units contain apparatus for selectively commencing an address transfer on the bus to one of the storage units during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors have means for monitoring the bus in order to determine whether an address on the bus has been transferred to the first or the second storage unit during a particular transfer interval. The address transfer apparatus further includes apparatus responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units to thus achieve alternating interleaving between storage units.

Abstract: A tandem axle suspension has frame supporting bracket assemblies on opposite sides. Each bracket assembly is connected through springs and torque rods to tandem axle assemblies. Lower torque rods are connected to outer ends of lower brackets. Inner ends of the lower brackets have upward box-like extensions which fit into complementary recesses in lower ends of the main frame supporting bracket. Shear forces which tend to separate the lower brackets from the main brackets, such as during heavy braking, are withstood by the projections and recesses. Crossover tubes fit within lower semicylindrical cavities in the lower brackets and cap plates with complementary upward facing semicylindrical cavities are fastened to the lower brackets to hold the crossover tubes.