Patents by Inventor Charles Gealer
Charles Gealer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11217516Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.Type: GrantFiled: December 21, 2018Date of Patent: January 4, 2022Assignee: Intel CorporationInventors: Sriram Muthukumar, Charles A. Gealer
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Patent number: 10555417Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.Type: GrantFiled: February 20, 2019Date of Patent: February 4, 2020Assignee: Intel CorporationInventors: Damion Searls, Weston C. Roth, Margaret D. Ramirez, James D. Jackson, Rainer E. Thomas, Charles A. Gealer
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Publication number: 20190182958Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.Type: ApplicationFiled: February 20, 2019Publication date: June 13, 2019Inventors: Damion SEARLS, Weston C. ROTH, Margaret D. RAMIREZ, James D. JACKSON, Rainer E. THOMAS, Charles A. GEALER
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Publication number: 20190148275Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.Type: ApplicationFiled: December 21, 2018Publication date: May 16, 2019Inventors: Sriram MUTHUKUMAR, Charles A. GEALER
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Patent number: 10251273Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.Type: GrantFiled: September 8, 2008Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Damion Searls, Weston C. Roth, Margaret D. Ramirez, James D. Jackson, Rainer E. Thomas, Charles A. Gealer
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Patent number: 10186480Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.Type: GrantFiled: January 14, 2013Date of Patent: January 22, 2019Assignee: INTEL CORPORATIONInventors: Sriram Muthukumar, Charles A. Gealer
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Publication number: 20180263117Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.Type: ApplicationFiled: November 13, 2017Publication date: September 13, 2018Inventors: Sasha N. Oster, Robert L. Sankman, Charles Gealer, Omkar Karhade, John S. Guzek, Ravindranath V. Mahajan, James C. Matayabas, JR., Johanna M. Swan, Feras Eid, Shawna Liff, Timothy McIntosh, Telesphor Kamgaing, Adel A. Elsherbini, Kemal Aygun
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Patent number: 9842832Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.Type: GrantFiled: June 15, 2016Date of Patent: December 12, 2017Assignee: Intel CorporationInventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
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Patent number: 9820384Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.Type: GrantFiled: December 11, 2013Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Sasha Oster, Robert L. Sankman, Charles Gealer, Omkar Karhade, John S. Guzek, Ravi V. Mahajan, James C. Matayabas, Jr., Johanna Swan, Feras Eid, Shawna Liff, Timothy McIntosh, Telesphor Kamgaing, Adel Elsherbini, Kemal Aygun
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Patent number: 9666549Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.Type: GrantFiled: October 9, 2015Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Chia-Pin Chiu, Xiaorong Xiong, Linda Zhang, Robert Nickerson, Charles Gealer
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Patent number: 9617148Abstract: Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermetically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.Type: GrantFiled: June 8, 2016Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Qing Ma, Johanna M. Swan, Min Tao, Charles A. Gealer, Edward T. Zarbock
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Publication number: 20170012029Abstract: An apparatus including a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; and a decoupling capacitor coupled to the TSV's. A method including providing a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; coupling a decoupling capacitor to the backside of the die. An apparatus including a computing device including a package including a microprocessor including a device side and a backside with through silicon vias (TSV's) extending from the device side to the backside, and a decoupling capacitor coupled to the backside of the die; and a printed circuit board, wherein the package is coupled to the printed circuit board.Type: ApplicationFiled: March 28, 2014Publication date: January 12, 2017Inventors: William J. LAMBERT, Robert L. SANKMAN, Tyler N. OSBORN, Charles A. GEALER
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Publication number: 20160300824Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.Type: ApplicationFiled: June 15, 2016Publication date: October 13, 2016Applicant: Intel CorporationInventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
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Publication number: 20160280539Abstract: Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermetically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Inventors: Qing MA, Johanna M. SWAN, Min TAO, Charles A. GEALER, Edward T. ZARBOCK
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Patent number: 9397071Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.Type: GrantFiled: December 11, 2013Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
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Patent number: 9368429Abstract: Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.Type: GrantFiled: September 28, 2012Date of Patent: June 14, 2016Assignee: Intel CorporationInventors: Qing Ma, Johanna M. Swan, Min Tao, Charles A. Gealer, Edward A. Zarbock
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Publication number: 20160043056Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet is over the interconnect areas of the first and the second die. Conductive vias in the dielectric sheet connect with pads of the interconnect areas. A build-up layer over the dielectric sheet includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias. The dies are mounted to a package substrate through the build-up layers, and a package cover is over the dies, the dielectric sheet, and the build-up layer.Type: ApplicationFiled: October 19, 2015Publication date: February 11, 2016Applicant: INTEL CORPORATIONInventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
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Publication number: 20160043049Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.Type: ApplicationFiled: October 9, 2015Publication date: February 11, 2016Inventors: Chia-Pin Chiu, Xiaorong Xiong, Linda Zhang, Robert Nickerson, Charles Gealer
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Patent number: 9177831Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.Type: GrantFiled: September 30, 2013Date of Patent: November 3, 2015Assignee: Intel CorporationInventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
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Patent number: 9159690Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. A package can include a chip package situated below a lower surface of a first substrate, the package including a die situated on a top surface of a second substrate, a molding disposed over the upper surface of the second substrate, the molding extending over the second die and including an opening extending from an upper surface of the molding towards an upper surface of the second substrate, wherein the opening is configured to admit at least a portion of the solder ball, and a solder column electrically and mechanically coupled to the second substrate, situated in the opening, conforming to the cylinder, and including at least two layers of solder with flux therebetween.Type: GrantFiled: September 25, 2013Date of Patent: October 13, 2015Assignee: Intel CorporationInventors: Chia-Pin Chiu, Xiaorong Xiong, Linda Zhang, Robert Nickerson, Charles Gealer