Patents by Inventor Charles Giefer
Charles Giefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11366588Abstract: A fabric interface apparatus, including: a fabric interface logic to communicatively couple to a fabric; a data interface to communicatively couple to a compute platform including memory resources in at least two memory tiers; and a tier-aware read/write engine (TARWE) to: receive an incoming packet via the fabric; parse a header of the incoming packet to identify a hint for directing the incoming packet to a preferred memory tier; and write the incoming packet to the preferred memory tier.Type: GrantFiled: July 3, 2017Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Francesc Guim Bernat, Nicolae O. Popovici, Charles A. Giefer, Gaspar Mora Porta, Thomas Willhalm
-
Patent number: 11172016Abstract: A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node.Type: GrantFiled: March 30, 2017Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Karl P. Brummel, Charles A. Giefer, Nathan S. Miller, Keith D. Underwood
-
Patent number: 10963183Abstract: Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.Type: GrantFiled: March 20, 2017Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: James Dinan, Keith D. Underwood, Sayantan Sur, Charles A. Giefer, Mario Flajslik
-
Patent number: 10693818Abstract: Packet tracking techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a tracking component for execution by the circuitry to, in response to a request of an initiator device to establish a packet transfer session, determine whether tracking information for the packet transfer session can be locally maintained and in response to a determination that the tracking information for the packet transfer session cannot be locally maintained, identify one or more tracking parameters for retention at the initiator device, and a communication component for execution by the circuitry to send an acceptance message to grant the request of the initiator device to establish the packet transfer session, the acceptance message to indicate a request for retention of the one or more tracking parameters. Other embodiments are described and claimed.Type: GrantFiled: November 13, 2018Date of Patent: June 23, 2020Assignee: INTEL CORPORATIONInventors: Keith D. Underwood, Charles A. Giefer
-
Patent number: 10505848Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.Type: GrantFiled: December 24, 2015Date of Patent: December 10, 2019Assignee: INTEL CORPORATIONInventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
-
Publication number: 20190268287Abstract: Packet tracking techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a tracking component for execution by the circuitry to, in response to a request of an initiator device to establish a packet transfer session, determine whether tracking information for the packet transfer session can be locally maintained and in response to a determination that the tracking information for the packet transfer session cannot be locally maintained, identify one or more tracking parameters for retention at the initiator device, and a communication component for execution by the circuitry to send an acceptance message to grant the request of the initiator device to establish the packet transfer session, the acceptance message to indicate a request for retention of the one or more tracking parameters. Other embodiments are described and claimed.Type: ApplicationFiled: November 13, 2018Publication date: August 29, 2019Applicant: Intel CorporationInventors: KEITH D. UNDERWOOD, CHARLES A. GIEFER
-
Patent number: 10348634Abstract: Technologies for tracking out-of-order network packets include a target computing node coupled to a source computing node via a communication channel. The target computing node is configured to allocate a small window in memory in which to store a bit mask corresponding to a number of out-of-order network packets received from the source computing node via the communication channel. The target computing node is further configured to update the bit mask in the small window upon receiving an out-of-order network packet from the source computing node. The target computing node is additionally configured to allocate a large window in memory in response to a determination the size of the bit mask is larger than the size of the small window, store the bit mask in the large window, and store a pointer to the large window in the small window. Other embodiments are described and claimed.Type: GrantFiled: December 22, 2015Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Keith D. Underwood, Charles A Giefer, Bruce M. Pirie, Karl P. Brummel
-
Patent number: 10320710Abstract: Methods, apparatus, and systems for reliable replication mechanisms based on active-passive HFI protocols build on top of non-reliable multicast fabric implementations. Under a first hardware-based scheme, a reliable replication mechanism is (primarily) implemented via Host Fabric Interfaces (HFIs) coupled to (or integrated in) nodes coupled to a non-reliable fabric. Under this approach, the HFIs take an active role in ensuring reliable delivery of multicast messages to each of multiple target nodes. Under a second hybrid software/hardware scheme, software running on nodes is responsible for determining whether target nodes have confirmed delivery of multicast messages and sending retry messages for cases in which delivery is not acknowledged within a timeout period. At the same time, the HFIs on the target nodes are responsible for generating reply messages containing acknowledgements rather than software running on the target nodes.Type: GrantFiled: September 25, 2015Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Francesc Guim Bernat, Charles A. Giefer, Raj K. Ramanujan, Robert G. Blankenship, Narayan Ranganathan
-
Publication number: 20190004701Abstract: A fabric interface apparatus, including: a fabric interface logic to communicatively couple to a fabric; a data interface to communicatively couple to a compute platform including memory resources in at least two memory tiers; and a tier-aware read/write engine (TARWE) to: receive an incoming packet via the fabric; parse a header of the incoming packet to identify a hint for directing the incoming packet to a preferred memory tier; and write the incoming packet to the preferred memory tier.Type: ApplicationFiled: July 3, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Francesc Guim Bernat, Nicolae O. Popovici, Charles A. Giefer, Gaspar Mora Porta, Thomas Willhalm
-
Patent number: 10128984Abstract: Packet tracking techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a tracking component for execution by the circuitry to, in response to a request of an initiator device to establish a packet transfer session, determine whether tracking information for the packet transfer session can be locally maintained and in response to a determination that the tracking information for the packet transfer session cannot be locally maintained, identify one or more tracking parameters for retention at the initiator device, and a communication component for execution by the circuitry to send an acceptance message to grant the request of the initiator device to establish the packet transfer session, the acceptance message to indicate a request for retention of the one or more tracking parameters. Other embodiments are described and claimed.Type: GrantFiled: December 21, 2015Date of Patent: November 13, 2018Assignee: INTEL CORPORATIONInventors: Keith D. Underwood, Charles A. Giefer
-
Patent number: 10129329Abstract: An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.Type: GrantFiled: October 13, 2015Date of Patent: November 13, 2018Assignee: Cray Inc.Inventors: Edwin L. Froese, Eric P. Lundberg, Igor Gorodetsky, Howard Pritchard, Charles Giefer, Robert L. Alverson, Duncan Roweth
-
Publication number: 20180287904Abstract: A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Karl P. Brummel, Charles A. Giefer, Nathan S. Miller, Keith D. Underwood
-
Publication number: 20180267742Abstract: Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.Type: ApplicationFiled: March 20, 2017Publication date: September 20, 2018Inventors: James Dinan, Keith D. Underwood, Sayantan Sur, Charles A. Giefer, Mario Flajslik
-
Patent number: 10044626Abstract: In an embodiment, an out-of-order, reliable, end-to-end protocol is provided that can enable direct user-level data placement and atomic operations between nodes of a multi-node network. The protocol may be optimized for low-loss environments such as High Performance Computing (HPC) applications, and may enable loss detection and de-duplication of packets through the use of a robust window state manager at a target node. A multi-node network implementing the protocol may have increased system reliability, packet throughput, and increased tolerance for adaptively routed traffic, while still allowing atomic operations to be idempotently applied directly to a user memory location.Type: GrantFiled: December 24, 2015Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Keith Underwood, Charles Giefer, Mark Debbage, Karl P. Brummel, Nathan Miller, Bruce Pirie
-
Publication number: 20170187637Abstract: In an embodiment, an out-of-order, reliable, end-to-end protocol is provided that can enable direct user-level data placement and atomic operations between nodes of a multi-node network. The protocol may be optimized for low-loss environments such as High Performance Computing (HPC) applications, and may enable loss detection and de-duplication of packets through the use of a robust window state manager at a target node. A multi-node network implementing the protocol may have increased system reliability, packet throughput, and increased tolerance for adaptively routed traffic, while still allowing atomic operations to be idempotently applied directly to a user memory location.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Keith D. UNDERWOOD, Charles A. GIEFER, Mark DEBBAGE, Karl P. BRUMMEL, Nathan S. MILLER, Bruce M. PIRIE
-
Publication number: 20170187630Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
-
Publication number: 20170180265Abstract: Technologies for tracking out-of-order network packets include a target computing node coupled to a source computing node via a communication channel. The target computing node is configured to allocate a small window in memory in which to store a bit mask corresponding to a number of out-of-order network packets received from the source computing node via the communication channel. The target computing node is further configured to update the bit mask in the small window upon receiving an out-of-order network packet from the source computing node. The target computing node is additionally configured to allocate a large window in memory in response to a determination the size of the bit mask is larger than the size of the small window, store the bit mask in the large window, and store a pointer to the large window in the small window. Other embodiments are described and claimed.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Keith D. Underwood, Charles A. Giefer, Bruce M. Pirie, Karl P. Brummel
-
Publication number: 20170180084Abstract: Packet tracking techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a tracking component for execution by the circuitry to, in response to a request of an initiator device to establish a packet transfer session, determine whether tracking information for the packet transfer session can be locally maintained and in response to a determination that the tracking information for the packet transfer session cannot be locally maintained, identify one or more tracking parameters for retention at the initiator device, and a communication component for execution by the circuitry to send an acceptance message to grant the request of the initiator device to establish the packet transfer session, the acceptance message to indicate a request for retention of the one or more tracking parameters. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Inventors: Keith D. Underwood, Charles A. Giefer
-
Publication number: 20170093756Abstract: Methods, apparatus, and systems for reliable replication mechanisms based on active-passive HFI protocols build on top of non-reliable multicast fabric implementations. Under a first hardware-based scheme, a reliable replication mechanism is (primarily) implemented via Host Fabric Interfaces (HFIs) coupled to (or integrated in) nodes coupled to a non-reliable fabric. Under this approach, the HFIs take an active role in ensuring reliable delivery of multicast messages to each of multiple target nodes. Under a second hybrid software/hardware scheme, software running on nodes is responsible for determining whether target nodes have confirmed delivery of multicast messages and sending retry messages for cases in which delivery is not acknowledged within a timeout period. At the same time, the HFIs on the target nodes are responsible for generating reply messages containing acknowledgements rather than software running on the target nodes.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Francesc Guim Bernat, Charles A. Giefer, Raj K. Ramanujan, Robert G. Blankenship, Narayan Ranganathan
-
Publication number: 20160077997Abstract: An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.Type: ApplicationFiled: October 13, 2015Publication date: March 17, 2016Inventors: Edwin L. Froese, Eric P. Lundberg, Igor Gorodetsky, Howard Pritchard, Charles Giefer, Robert L. Alverson, Duncan Roweth