Patents by Inventor Charles H. Field
Charles H. Field has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9606700Abstract: Disclosed herein are user interfaces and related systems and methods for selecting hierarchically arranged items in order to facilitate subsequent operations on an accumulation of such data selected from throughout a hierarchy. More specifically, a columnized user interface is disclosed that includes a final column containing an accumulation of items selected from various locations within the hierarchy. A user may interactively navigate throughout the hierarchy in one or more other columns, while selectively adding specific items from any such hierarchical locations in the final column for subsequent processing. Other tools may support grouping into favorites, recall of previous selections, or other operations to facilitate rapid creation and recreation of item groups for processing.Type: GrantFiled: March 8, 2013Date of Patent: March 28, 2017Assignee: Information Resources, Inc.Inventors: Kurt N. Schafer, Charles H. Field, Adam L. Fisher
-
Publication number: 20140258939Abstract: Disclosed herein are user interfaces and related systems and methods for selecting hierarchically arranged items in order to facilitate subsequent operations on an accumulation of such data selected from throughout a hierarchy. More specifically, a columnized user interface is disclosed that includes a final column containing an accumulation of items selected from various locations within the hierarchy. A user may interactively navigate throughout the hierarchy in one or more other columns, while selectively adding specific items from any such hierarchical locations in the final column for subsequent processing. Other tools may support grouping into favorites, recall of previous selections, or other operations to facilitate rapid creation and recreation of item groups for processing.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: Information Resources, Inc.Inventors: Kurt N. Schafer, Charles H. Field, Adam L. Fisher
-
Patent number: 8574994Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.Type: GrantFiled: October 22, 2010Date of Patent: November 5, 2013Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
-
Patent number: 8435852Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.Type: GrantFiled: July 30, 2012Date of Patent: May 7, 2013Assignee: HRL Laboratories, LLCInventor: Charles H. Fields, Jr.
-
Patent number: 8169001Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; depositing base metal on the entire surface; and removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD from 0.05 ?m to 0.7 ?m. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.Type: GrantFiled: November 4, 2010Date of Patent: May 1, 2012Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
-
Patent number: 8153532Abstract: The present invention improves the yield of integrated circuit manufacture by making the circuit more tolerant of varying thicknesses of the InterLayer Dielectric prior to metallization and interconnection. The sensitivity to the thickness of the ILD is reduced by first coating the devices with an etch stop layer, exposing the areas of the devices where interconnections will be made, selectively etching away the etch stop layer over the interconnection areas, adding the Interlayer Dielectric and then finally etching away the ILD to expose the contacts and continuing the processing through interconnection of the devices.Type: GrantFiled: December 4, 2008Date of Patent: April 10, 2012Assignee: HRL Laboratories, LLCInventor: Charles H Fields
-
Patent number: 7875523Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.Type: GrantFiled: June 16, 2005Date of Patent: January 25, 2011Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
-
Patent number: 7851319Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; depositing base metal on the entire surface; and removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD from 0.05 ?m to 0.7 ?m. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.Type: GrantFiled: May 6, 2008Date of Patent: December 14, 2010Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
-
Patent number: 7598148Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.Type: GrantFiled: October 15, 2004Date of Patent: October 6, 2009Inventor: Charles H. Fields
-
Patent number: 7396731Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; depositing base metal on the entire surface; and removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD from 0.05 ?m to 0.7 ?m. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.Type: GrantFiled: October 15, 2004Date of Patent: July 8, 2008Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
-
Patent number: 6916720Abstract: A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.Type: GrantFiled: July 5, 2002Date of Patent: July 12, 2005Assignee: Hughes Electronics CorporationInventors: Kursad Kiziloglu, Charles H. Fields, Adele E. Schmitz
-
Publication number: 20020182818Abstract: A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.Type: ApplicationFiled: July 5, 2002Publication date: December 5, 2002Inventors: Kursad Kiziloglu, Charles H. Fields, Adele E. Schmitz