Patents by Inventor Charles H. Fields

Charles H. Fields has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8574994
    Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: November 5, 2013
    Assignee: HRL Laboratories, LLC
    Inventor: Charles H. Fields
  • Patent number: 8169001
    Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; depositing base metal on the entire surface; and removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD from 0.05 ?m to 0.7 ?m. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: May 1, 2012
    Assignee: HRL Laboratories, LLC
    Inventor: Charles H. Fields
  • Patent number: 7875523
    Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: January 25, 2011
    Assignee: HRL Laboratories, LLC
    Inventor: Charles H. Fields
  • Patent number: 7851319
    Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; depositing base metal on the entire surface; and removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD from 0.05 ?m to 0.7 ?m. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: December 14, 2010
    Assignee: HRL Laboratories, LLC
    Inventor: Charles H. Fields
  • Patent number: 7598148
    Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: October 6, 2009
    Inventor: Charles H. Fields
  • Patent number: 7396731
    Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; depositing base metal on the entire surface; and removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD from 0.05 ?m to 0.7 ?m. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: July 8, 2008
    Assignee: HRL Laboratories, LLC
    Inventor: Charles H. Fields
  • Patent number: 6916720
    Abstract: A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: July 12, 2005
    Assignee: Hughes Electronics Corporation
    Inventors: Kursad Kiziloglu, Charles H. Fields, Adele E. Schmitz
  • Publication number: 20020182818
    Abstract: A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.
    Type: Application
    Filed: July 5, 2002
    Publication date: December 5, 2002
    Inventors: Kursad Kiziloglu, Charles H. Fields, Adele E. Schmitz