Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: A simple CMOS voltage reference circuit develops a reference voltage from the sum of the threshold voltages of a pair of complementary devices. In a p-type substrate a p-channel device is formed in an isolated n-type well, with the well tied to the source at the reference node. The drain is coupled to the drain of a complementary n-channel device. An additional p-channel device functions as a current source. The voltage reference circuit may be advantageously cascaded to improve stability and insensitivity to the power supply voltage.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: An MOS comparator circuit for sensing small voltage differences between two inputs is disclosed. The response time of the comparator circuit is improved by providing both a differential amplifier circuit and an output circuit with faster response times. The response time of the differential comparator circuit is improved by preventing the current-mirror from turning off. The response time of the output circuit is improved by limiting the input voltage to the inverter of the output circuit to a range of slightly greater than the balance-point voltage and slightly less than the balance-point voltage of the inverter.The difference between the response of the comparator circuit to large amplitude input voltages and small amplitude input voltages is also improved.

Abstract: A switched capacitor array (20) for use in a digital-to-analog converter (10), an analog-to-digital converter (60), or other digitally controlled circuit is disclosed. The array includes a plurality of switched capacitors (C(0) through C(15)) of substantially identical value, each having a switched terminal. Logic circuitry (17) responsive to a digital input signal (A) having a value N provides a logic output signal indicative of the digital input signal. Gating circuitry (40) responsive to the logic output signal switches the switched terminal of a selected switched capacitor to an analog signal provided by a digital-to-analog converter stage of lesser weight, and sequentially switches the switched terminals of a predetermined number of the switched capacitors to a predetermined voltage. The selected capacitor and such predetermined number of capacitors are determined by the value N of the digital input signal.

Abstract: The MOS switch described herein includes first and second MOS devices serially connected in a common substrate. Each device includes source, drain and channel regions which are biased to conduction in series between input and output terminals of the switch in its "on" or conductive state. The novel device connection prevents any pn junction in either MOS device from becoming forward biased. This action, in turn, prevents any parasitic bipolar transistor action in either device after the MOS switch turns off. This latter operational feature eliminates the need for a fourth terminal through which a DC bias potential is applied to either MOS device, and thus undesirable shifts in threshold voltage produced by such DC bias are eliminated.

Abstract: A switched capacitor circuit for use in a digital-to-analog converter, an analog-to-digital converter, or other digitally controlled circuit is disclosed. The switched capacitor circuit includes first and second arrays (30, 40) of switched capacitors of substantially identical value, each capacitor having a switched terminal. The switched capacitor circuit further includes a decoding circuit (20) responsive to a digital input having a decimal value N for providing control signals for each of the capacitor arrays. Logic circuitry (33, 43, GC(I)) responsive to the control signals is included for sequentially switching the switched terminals of L and M capacitors respectively of the first and second switched capacitor arrays in a predetermined sequence so as to maintain the geometrical centroid of the switched capacitors at a substantially constant location, where the sum of L and M is equal to N.

Abstract: An active biquadratic notch filter having first integrating circuitry for providing a first integration signal and further having second integrating circuitry responsive to the first integration signal for providing a filter output. The first integrating circuitry includes at least one operational amplifier. The notch filter further includes compensation circuitry for compensating the limitation on notch frequency attenuation resulting from current lag introduced by the at least one operational amplifier of the first integrating circuitry.

Abstract: We disclose and claim a novel high efficiency oscillator circuit and method of operation wherein output signal distortion is minimized by applying the weighted sum of currents flowing in an input complementary transistor pair to each transistor in an output complementary pair. This operation is accomplished using a novel summing current mirror stage to interconnect the input and output complementary pairs, and the channel width-to-length, W/L, ratios of transistors in the mirror stage sets the value of the weighted sum of currents applied to the complementary pair output stage.

Abstract: An operational amplifier circuit including an output stage which requires relatively low operating current to achieve a desired transconductance in order to permit improved driving of a capacitive load.

Abstract: An improved output circuit for an operational amplifier which is controlled to operate in one of two modes. In the first mode, the output of the operational amplifier tracks a reference signal or ground. In the second mode, the output of the operational amplifier tracks the level of a time varying second voltage signal. The improvement consists of replacing the stabilization capacitor of prior art output circuits with a pair of stabilization capacitors connected in parallel. Each of the pair of capacitors has an associated series connected switch for switching the capacitor into and out of the circuit. The switches are operated by a respective one of a pair of external non-overlapping clock pulse trains so as to not be closed simultaneously.

Abstract: In the present invention, channel charge compensation is achieved in a MOS switch comprising two MOSFETs connected in parallel and a compensating MOSFET placed on the semiconductive substrate in precise symmetry with the two switching FETs, each of the FETs being designed to have the same channel charge storing capacity. Accordingly, first order variations in oxide thickness or in gate width across the surface of the semiconductive substrate do not affect the accuracy with which channel charge is compensated in the invention. The compensating FET is switched in complementary fashion with the two switching FETs so that it absorbs one-half of the channel charge expelled from the switching FETs when they are turned off, thus preventing this charge from upsetting other components in the circuit such as precision storage capacitors connected to the switch.

Abstract: The auto-zeroing technique of this invention comprises two steps. In the first step, the differential amplifier output and negative input are shorted together and the resulting amplifier offset output voltage is stored across an input capacitor and a feedback capacitor, the input capacitor being connected between the amplifier negative input and a voltage source to be sampled and the feedback capacitor being connected between the amplifier negative input and ground. In the second step, the direct connection between the amplifier output and negative input is removed and the feedback capacitor is reconnected between the amplifier output and negative input in a feedback loop. At this time, a voltage of the same magnitude and opposite polarity as the original amplifier offset output voltage is applied as negative feedback across the amplifier, so that the amplifier offset output voltage is precisely zeroed. In an alternative embodiment, the connection and reconnection steps are performed at a frequency f.sub.

Abstract: A very low current Pierce oscillator has two pairs of complementary field-effect transistors (FET's) and a two-terminal quartz crystal. The gates of the first complementary FET pair are coupled through individual capacitors to one terminal of the quartz crystal, their drains being connected together and to the other quartz crystal terminal. Current flow through the crystal oscillator is minimized by a novel oscillator bias loop connected between the gates of the first FET pair. Amplification is provided by the second FET pair which have a commonly connected drain comprising the oscillator output node. The gates of the second FET pair are each connected to a respective one of the gates of the first FET pair. The oscillator bias loop minimizes the source-to-drain current through the first FET pair by reducing the P-channel FET gate voltage in response to the source-to-drain current.

Abstract: An analog-to-digital converter, finding particular application in a multichannel pulse height analyzer, includes means for digitizing the analog input in two conversion steps. To digitize the input to 13 bits, a 7-bit digital to analog converter (DAC) with a 7-bit up-down counter is used. During the first conversion step which is a coarse conversion, the input, V.sub.I, is compared with the DAC output, V.sub.L and the 7-bits of the counter are set by successive approximation. Thereafter, after settling, the DAC output is driven twice toward V.sub.I. The output of an amplifier of a gain 2.sup.7 is stored after each change of the DAC in one of two storage and hold circuits, depending on the polarity of the amplifier output. Then, the content of the 7-bit counter is transferred to the 7 higher order bits of a 14-bit buffer counter. Then, the fine conversion step is performed by successive approximation.